libraries/io/ddr/src/vhdl/io_ddr_driver.vhd · a8775752ff87f9395f892196b9c884b44cb17756 · RTSD / HDL · GitLab

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9 years ago
bd490884
Corrected asserting ctlr_mosi.burstbegin for only one clock cycle as specified... · bd490884
Eric Kooistra authored 9 years ago
```
Corrected asserting ctlr_mosi.burstbegin for only one clock cycle as specified in the uniphy emi_ip.pdf manual.
```
bd490884

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Corrected asserting ctlr_mosi.burstbegin for only one clock cycle as specified...
Eric Kooistra authored 9 years ago
```
Corrected asserting ctlr_mosi.burstbegin for only one clock cycle as specified in the uniphy emi_ip.pdf manual.
```

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