hdllib.cfg

hdl_lib_name = io_ddr
hdl_library_clause_name = io_ddr_lib
hdl_lib_uses = technology tech_ddr tech_ddr3 common dp diagnostics 
hdl_lib_technology = 

build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR

modelsim_compile_ip_files =
    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
    $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl

synth_files =
    src/vhdl/io_ddr_driver_flush_ctrl.vhd
    src/vhdl/io_ddr_driver.vhd
    src/vhdl/io_ddr_cross_domain.vhd
    src/vhdl/io_ddr.vhd

test_bench_files = 
    tb/vhdl/tb_io_ddr.vhd
    tb/vhdl/tb_tb_io_ddr.vhd

modelsim_search_libraries =
# stratixiv only
#    altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
#    altera     lpm     sgate     altera_mf     altera_lnsim     stratixiv     stratixiv_hssi     stratixiv_pcie_hip
# arria10 only
#    altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
#    altera     lpm     sgate     altera_mf     altera_lnsim     twentynm     twentynm_hssi     twentynm_hip
# both (will yield errors if the technology library is not available in simulator but these errors can be ignored)
    altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
    altera     lpm     sgate     altera_mf     altera_lnsim     stratixiv     stratixiv_hssi     stratixiv_pcie_hip     twentynm     twentynm_hssi     twentynm_hip