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Reinier van der Walle authoredReinier van der Walle authored
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tech_complex_mult.vhd 13.80 KiB
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
--
-- Author : E. Kooistra
-- Purpose : Wrapper for complex multiplier IP
-- Decription :
--
-- Calculate complex product:
--
-- (ar + j*ai) * (br + j*bi) = (ar*br - ai*bi) + j *(ar*bi + ai*br)
-- = pr + j * pi
--
-- Assume IP is generated for complex product width for pr, pi of:
--
-- c_dsp_prod_w = 2*c_dsp_dat_w.
--
-- It is not necessary to support product width 2*c_dsp_dat_w + 1,
-- because this +1 bit is only needed for pi in case ar = ai = br = bi
-- = min, where
--
-- min = -2**(c_dsp_dat_w-1)
-- max = 2**(c_dsp_dat_w-1) - 1.
--
-- The largest value for pi = min**2 + min**2.
-- The largest value for pr = min**2 - min*max < largest pi.
--
-- The largest pi = 2 * min**2 = 2**(c_dsp_dat_w-1), so it just does not
-- fit in c_dsp_prod_w, but largest pi - 1 = 2**(c_dsp_dat_w-1) - 1 does
-- fit, so all other input values fit. In DSP systems the input value
-- (min + j*min) typically never occurs.
--
-- Example: g_in_a_w = 3 bit:
-- --> min = -4
-- c_dsp_prod_w = 6
-- --> largest pi = 32
-- --> largest pi - 1 = 31 = 2**(c_dsp_prod_w-1) - 1
--
LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE common_lib.common_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE work.tech_mult_component_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_mult_lib;
--LIBRARY ip_arria10_mult_lib;
--LIBRARY ip_arria10_mult_rtl_lib;
LIBRARY ip_arria10_complex_mult_altmult_complex_150;
LIBRARY ip_arria10_e1sg_complex_mult_altmult_complex_180;
LIBRARY ip_arria10_e2sg_complex_mult_altmult_complex_1910;LIBRARY ip_arria10_complex_mult_rtl_lib;
LIBRARY ip_arria10_complex_mult_rtl_canonical_lib;
ENTITY tech_complex_mult IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_variant : STRING := "IP";
g_in_a_w : POSITIVE;
g_in_b_w : POSITIVE;
g_out_p_w : POSITIVE; -- default use g_out_p_w = g_in_a_w+g_in_b_w = c_prod_w
g_conjugate_b : BOOLEAN := FALSE;
g_pipeline_input : NATURAL := 1; -- 0 or 1
g_pipeline_product : NATURAL := 0; -- 0 or 1
g_pipeline_adder : NATURAL := 1; -- 0 or 1
g_pipeline_output : NATURAL := 1 -- >= 0
);
PORT (
rst : IN STD_LOGIC := '0';
clk : IN STD_LOGIC;
clken : IN STD_LOGIC := '1';
in_ar : IN STD_LOGIC_VECTOR(g_in_a_w-1 DOWNTO 0);
in_ai : IN STD_LOGIC_VECTOR(g_in_a_w-1 DOWNTO 0);
in_br : IN STD_LOGIC_VECTOR(g_in_b_w-1 DOWNTO 0);
in_bi : IN STD_LOGIC_VECTOR(g_in_b_w-1 DOWNTO 0);
result_re : OUT STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0);
result_im : OUT STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0)
);
END tech_complex_mult;
ARCHITECTURE str of tech_complex_mult is
CONSTANT c_dsp_dat_w : NATURAL := sel_a_b(g_in_a_w <= c_dsp_mult_18_w, c_dsp_mult_18_w, c_dsp_mult_27_w); -- g_in_a_w = g_in_b_w
CONSTANT c_dsp_prod_w : NATURAL := 2*c_dsp_dat_w;
SIGNAL ar : STD_LOGIC_VECTOR(c_dsp_dat_w-1 DOWNTO 0);
SIGNAL ai : STD_LOGIC_VECTOR(c_dsp_dat_w-1 DOWNTO 0);
SIGNAL br : STD_LOGIC_VECTOR(c_dsp_dat_w-1 DOWNTO 0);
SIGNAL bi : STD_LOGIC_VECTOR(c_dsp_dat_w-1 DOWNTO 0);
SIGNAL mult_re : STD_LOGIC_VECTOR(c_dsp_prod_w-1 DOWNTO 0);
SIGNAL mult_im : STD_LOGIC_VECTOR(c_dsp_prod_w-1 DOWNTO 0);
BEGIN
-----------------------------------------------------------------------------
-- IP variants for <= 18 bit
-----------------------------------------------------------------------------
gen_ip_stratixiv_ip : IF g_variant="IP" AND g_technology=c_tech_stratixiv AND c_dsp_dat_w <= c_dsp_mult_18_w GENERATE
-- Adapt DSP input widths
ar <= RESIZE_SVEC(in_ar, c_dsp_mult_18_w);
ai <= RESIZE_SVEC(in_ai, c_dsp_mult_18_w);
br <= RESIZE_SVEC(in_br, c_dsp_mult_18_w);
bi <= RESIZE_SVEC(in_bi, c_dsp_mult_18_w) WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_18_w);
u0 : ip_stratixiv_complex_mult
PORT MAP (
aclr => rst,
clock => clk,
dataa_imag => ai,
dataa_real => ar,
datab_imag => bi,
datab_real => br,
ena => clken,
result_imag => mult_im,
result_real => mult_re
);
-- Back to true input widths and then resize for output width
result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
result_im <= RESIZE_SVEC(mult_im, g_out_p_w); END GENERATE;
gen_ip_arria10_ip : IF g_variant="IP" AND g_technology=c_tech_arria10 AND c_dsp_dat_w <= c_dsp_mult_18_w GENERATE
-- Adapt DSP input widths
ar <= RESIZE_SVEC(in_ar, c_dsp_mult_18_w);
ai <= RESIZE_SVEC(in_ai, c_dsp_mult_18_w);
br <= RESIZE_SVEC(in_br, c_dsp_mult_18_w);
bi <= RESIZE_SVEC(in_bi, c_dsp_mult_18_w) WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_18_w);
u0 : ip_arria10_complex_mult
PORT MAP (
aclr => rst,
clock => clk,
dataa_imag => ai,
dataa_real => ar,
datab_imag => bi,
datab_real => br,
ena => clken,
result_imag => mult_im,
result_real => mult_re
);
-- Back to true input widths and then resize for output width
result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
END GENERATE;
gen_ip_arria10_e1sg_ip : IF g_variant="IP" AND g_technology=c_tech_arria10_e1sg AND c_dsp_dat_w <= c_dsp_mult_18_w GENERATE
-- Adapt DSP input widths
ar <= RESIZE_SVEC(in_ar, c_dsp_mult_18_w);
ai <= RESIZE_SVEC(in_ai, c_dsp_mult_18_w);
br <= RESIZE_SVEC(in_br, c_dsp_mult_18_w);
bi <= RESIZE_SVEC(in_bi, c_dsp_mult_18_w) WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_18_w);
u0 : ip_arria10_e1sg_complex_mult
PORT MAP (
aclr => rst,
clock => clk,
dataa_imag => ai,
dataa_real => ar,
datab_imag => bi,
datab_real => br,
ena => clken,
result_imag => mult_im,
result_real => mult_re
);
-- Back to true input widths and then resize for output width
result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
END GENERATE;
gen_ip_arria10_e2sg_ip : IF g_variant="IP" AND g_technology=c_tech_arria10_e2sg AND c_dsp_dat_w <= c_dsp_mult_18_w GENERATE
-- Adapt DSP input widths
ar <= RESIZE_SVEC(in_ar, c_dsp_mult_18_w);
ai <= RESIZE_SVEC(in_ai, c_dsp_mult_18_w);
br <= RESIZE_SVEC(in_br, c_dsp_mult_18_w);
bi <= RESIZE_SVEC(in_bi, c_dsp_mult_18_w) WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_18_w);
u0 : ip_arria10_e2sg_complex_mult
PORT MAP (
aclr => rst,
clock => clk,
dataa_imag => ai,
dataa_real => ar,
datab_imag => bi,
datab_real => br,
ena => clken,
result_imag => mult_im,
result_real => mult_re );
-- Back to true input widths and then resize for output width
result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
END GENERATE;
-----------------------------------------------------------------------------
-- IP variants for > 18 bit and <= 27 bit
-----------------------------------------------------------------------------
gen_ip_arria10_e1sg_ip_27b : IF g_variant="IP" AND g_technology=c_tech_arria10_e1sg AND c_dsp_dat_w > c_dsp_mult_18_w AND c_dsp_dat_w <= c_dsp_mult_27_w GENERATE
-- Adapt DSP input widths
ar <= RESIZE_SVEC(in_ar, c_dsp_mult_27_w);
ai <= RESIZE_SVEC(in_ai, c_dsp_mult_27_w);
br <= RESIZE_SVEC(in_br, c_dsp_mult_27_w);
bi <= RESIZE_SVEC(in_bi, c_dsp_mult_27_w) WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_27_w);
u0 : ip_arria10_e1sg_complex_mult_27b
PORT MAP (
aclr => rst,
clock => clk,
dataa_imag => ai,
dataa_real => ar,
datab_imag => bi,
datab_real => br,
ena => clken,
result_imag => mult_im,
result_real => mult_re
);
-- Back to true input widths and then resize for output width
result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
END GENERATE;
gen_ip_arria10_e2sg_ip_27b : IF g_variant="IP" AND g_technology=c_tech_arria10_e2sg AND c_dsp_dat_w > c_dsp_mult_18_w AND c_dsp_dat_w <= c_dsp_mult_27_w GENERATE
-- Adapt DSP input widths
ar <= RESIZE_SVEC(in_ar, c_dsp_mult_27_w);
ai <= RESIZE_SVEC(in_ai, c_dsp_mult_27_w);
br <= RESIZE_SVEC(in_br, c_dsp_mult_27_w);
bi <= RESIZE_SVEC(in_bi, c_dsp_mult_27_w) WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_27_w);
--u0 : ip_arria10_e2sg_complex_mult_27b
--PORT MAP (
-- aclr => rst,
-- clock => clk,
-- dataa_imag => ai,
-- dataa_real => ar,
-- datab_imag => bi,
-- datab_real => br,
-- ena => clken,
-- result_imag => mult_im,
-- result_real => mult_re
--);
-- Back to true input widths and then resize for output width
result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
END GENERATE;
-----------------------------------------------------------------------------
-- RTL variants that can infer multipliers for a technology, fits all widths
-----------------------------------------------------------------------------
gen_ip_stratixiv_rtl : IF g_variant="RTL" AND g_technology=c_tech_stratixiv GENERATE
u0 : ip_stratixiv_complex_mult_rtl
GENERIC MAP (
g_in_a_w => g_in_a_w,
g_in_b_w => g_in_b_w, g_out_p_w => g_out_p_w,
g_conjugate_b => g_conjugate_b,
g_pipeline_input => g_pipeline_input,
g_pipeline_product => g_pipeline_product,
g_pipeline_adder => g_pipeline_adder,
g_pipeline_output => g_pipeline_output
)
PORT MAP (
rst => rst,
clk => clk,
clken => clken,
in_ar => in_ar,
in_ai => in_ai,
in_br => in_br,
in_bi => in_bi,
result_re => result_re,
result_im => result_im
);
END GENERATE;
-- RTL variant is the same for unb2, unb2a and unb2b
gen_ip_arria10_rtl : IF g_variant="RTL" AND (g_technology=c_tech_arria10 OR
g_technology=c_tech_arria10_e3sge3 OR
g_technology=c_tech_arria10_e1sg OR
g_technology=c_tech_arria10_e2sg) GENERATE
u0 : ip_arria10_complex_mult_rtl
GENERIC MAP (
g_in_a_w => g_in_a_w,
g_in_b_w => g_in_b_w,
g_out_p_w => g_out_p_w,
g_conjugate_b => g_conjugate_b,
g_pipeline_input => g_pipeline_input,
g_pipeline_product => g_pipeline_product,
g_pipeline_adder => g_pipeline_adder,
g_pipeline_output => g_pipeline_output
)
PORT MAP (
rst => rst,
clk => clk,
clken => clken,
in_ar => in_ar,
in_ai => in_ai,
in_br => in_br,
in_bi => in_bi,
result_re => result_re,
result_im => result_im
);
END GENERATE;
-- RTL variant is the same for unb2, unb2a and unb2b
gen_ip_arria10_rtl_canonical : IF g_variant="RTL_C" AND (g_technology=c_tech_arria10 OR
g_technology=c_tech_arria10_e3sge3 OR
g_technology=c_tech_arria10_e1sg OR
g_technology=c_tech_arria10_e2sg) GENERATE
-- support g_conjugate_b
bi <= in_bi WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), g_in_b_w);
u0 : ip_arria10_complex_mult_rtl_canonical
GENERIC MAP (
g_in_a_w => g_in_a_w,
g_in_b_w => g_in_b_w,
g_out_p_w => g_out_p_w,
g_pipeline_input => g_pipeline_input,
g_pipeline_product => g_pipeline_product,
g_pipeline_adder => g_pipeline_adder,
g_pipeline_output => g_pipeline_output
)
PORT MAP (
rst => rst,
clk => clk, clken => clken,
in_ar => in_ar,
in_ai => in_ai,
in_br => in_br,
in_bi => bi,
result_re => result_re,
result_im => result_im
);
END GENERATE;
end str;