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Commit 6504afb8 authored by Reinier van der Walle's avatar Reinier van der Walle
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Added complex multiplier 27 bits IP

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1 merge request!147L2SDP-494
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libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd
+ 4
− 4
View file @ 6504afb8
......@@ -49,10 +49,10 @@ BEGIN
u_ip_18b : ENTITY work.tb_common_complex_mult GENERIC MAP ("IP", 18, FALSE, 1, 0, 1, 1);
u_ip_18b_conj : ENTITY work.tb_common_complex_mult GENERIC MAP ("IP", 18, TRUE, 1, 0, 1, 1);
--gen_27b : IF c_tech_select_default /= c_tech_stratixiv GENERATE
-- u_ip_27b : ENTITY work.tb_common_complex_mult GENERIC MAP ("IP", 27, FALSE, 1, 0, 1, 1);
-- u_ip_27b_conj : ENTITY work.tb_common_complex_mult GENERIC MAP ("IP", 27, TRUE, 1, 0, 1, 1);
--END GENERATE;
gen_27b : IF c_tech_select_default /= c_tech_stratixiv GENERATE
u_ip_27b : ENTITY work.tb_common_complex_mult GENERIC MAP ("IP", 27, FALSE, 1, 0, 1, 1);
u_ip_27b_conj : ENTITY work.tb_common_complex_mult GENERIC MAP ("IP", 27, TRUE, 1, 0, 1, 1);
END GENERATE;
-- RTL variants
u_rtl_18b : ENTITY work.tb_common_complex_mult GENERIC MAP ("RTL", 18, FALSE, 1, 0, 1, 1);
......
libraries/technology/ip_arria10_e1sg/altera_libraries/altmult_complex_180/compile_ip.tcl
+ 3
− 0
View file @ 6504afb8
......@@ -34,3 +34,6 @@ set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
vmap altmult_complex_180 ./work/
vcom "$IP_DIR/../altmult_complex_180/sim/ip_arria10_e1sg_complex_mult_altmult_complex_180_nkpx3mi.vhd"
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult_27b/sim"
vcom "$IP_DIR/../altmult_complex_180/sim/ip_arria10_e1sg_complex_mult_27b_altmult_complex_180_ylvsosy.vhd"
libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
+ 3
− 0
View file @ 6504afb8
......@@ -31,3 +31,6 @@
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult/sim"
vcom "$IP_DIR/ip_arria10_e1sg_complex_mult.vhd"
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult_27b/sim"
vcom "$IP_DIR/ip_arria10_e1sg_complex_mult_27b.vhd"
libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
+ 1
− 0
View file @ 6504afb8
......@@ -21,4 +21,5 @@ quartus_qip_files =
[generate_ip_libs]
qsys-generate_ip_files =
ip_arria10_e1sg_complex_mult.qsys
ip_arria10_e1sg_complex_mult_27b.ip
libraries/technology/ip_arria10_e1sg/complex_mult/ip_arria10_e1sg_complex_mult_27b.ip 0 → 100644
+ 431
− 0
View file @ 6504afb8
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>Intel Corporation</spirit:vendor>
<spirit:library>ip_arria10_e1sg_complex_mult_27b</spirit:library>
<spirit:name>altmult_complex_0</spirit:name>
<spirit:version>18.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>complex_input</spirit:name>
<spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
<spirit:slave></spirit:slave>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>dataa_real</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>dataa_real</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>dataa_imag</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>dataa_imag</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>datab_real</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>datab_real</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>datab_imag</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>datab_imag</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>clk</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>clock</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>aclr</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>aclr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ena</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ena</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>associatedClock</spirit:name>
<spirit:displayName>associatedClock</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>associatedReset</spirit:name>
<spirit:displayName>associatedReset</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>prSafe</spirit:name>
<spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
<spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>complex_output</spirit:name>
<spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
<spirit:slave></spirit:slave>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>result_real</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>result_real</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>result_imag</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>result_imag</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>associatedClock</spirit:name>
<spirit:displayName>associatedClock</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>associatedReset</spirit:name>
<spirit:displayName>associatedReset</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>prSafe</spirit:name>
<spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
<spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<altera:altera_assignments>
<spirit:parameters>
<spirit:parameter>
<spirit:name>ui.blockdiagram.direction</spirit:name>
<spirit:value spirit:format="string" spirit:id="ui.blockdiagram.direction">output</spirit:value>
</spirit:parameter>
</spirit:parameters>
</altera:altera_assignments>
</spirit:vendorExtensions>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>QUARTUS_SYNTH</spirit:name>
<spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
<spirit:modelName>altmult_complex</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>QUARTUS_SYNTH</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>dataa_real</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>26</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
<spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>dataa_imag</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>26</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
<spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>datab_real</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>26</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
<spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>datab_imag</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>26</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
<spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>clock</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
<spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>aclr</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
<spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>ena</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC</spirit:typeName>
<spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>result_real</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>53</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
<spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>result_imag</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>53</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
<spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:model>
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>Intel Corporation</spirit:vendor>
<spirit:library>ip_arria10_e1sg_complex_mult_27b</spirit:library>
<spirit:name>altmult_complex</spirit:name>
<spirit:version>18.0</spirit:version>
</altera:entity_info>
<altera:altera_module_parameters>
<spirit:parameters>
<spirit:parameter>
<spirit:name>DEVICE_FAMILY</spirit:name>
<spirit:displayName>Device family</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="DEVICE_FAMILY">Arria 10</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CBX_AUTO_BLACKBOX</spirit:name>
<spirit:displayName>CBX_AUTO_BLACKBOX</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="CBX_AUTO_BLACKBOX">ALL</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>WIDTH_A</spirit:name>
<spirit:displayName>How wide should the A input buses be?</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="WIDTH_A">27</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>WIDTH_B</spirit:name>
<spirit:displayName>How wide should the B input buses be?</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="WIDTH_B">27</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>WIDTH_RESULT</spirit:name>
<spirit:displayName>How wide should the 'result' output bus be?</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="WIDTH_RESULT">54</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>REPRESENTATION_A</spirit:name>
<spirit:displayName>What is the representation format for A inputs?</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="REPRESENTATION_A">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>REPRESENTATION_B</spirit:name>
<spirit:displayName>What is the representation format for B inputs?</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="REPRESENTATION_B">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>GUI_DYNAMIC_COMPLEX</spirit:name>
<spirit:displayName>Dynamic Complex Mode</spirit:displayName>
<spirit:value spirit:format="bool" spirit:id="GUI_DYNAMIC_COMPLEX">false</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>IMPLEMENTATION_STYLE</spirit:name>
<spirit:displayName>Which implementation style should be used?</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="IMPLEMENTATION_STYLE">AUTO</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>PIPELINE</spirit:name>
<spirit:displayName>Output latency</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="PIPELINE">3</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>GUI_CLEAR_TYPE</spirit:name>
<spirit:displayName>Clear Signal Type</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="GUI_CLEAR_TYPE">ACLR</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>GUI_USE_CLKEN</spirit:name>
<spirit:displayName>Create a Clock Enable input?</spirit:displayName>
<spirit:value spirit:format="bool" spirit:id="GUI_USE_CLKEN">true</spirit:value>
</spirit:parameter>
</spirit:parameters>
</altera:altera_module_parameters>
<altera:altera_system_parameters>
<spirit:parameters>
<spirit:parameter>
<spirit:name>device</spirit:name>
<spirit:displayName>Device</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="device">10AX115S2F45E1SG</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>deviceFamily</spirit:name>
<spirit:displayName>Device family</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>deviceSpeedGrade</spirit:name>
<spirit:displayName>Device Speed Grade</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>generationId</spirit:name>
<spirit:displayName>Generation Id</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>bonusData</spirit:name>
<spirit:displayName>bonusData</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="bonusData">bonusData
{
element altmult_complex_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>hideFromIPCatalog</spirit:name>
<spirit:displayName>Hide from IP Catalog</spirit:displayName>
<spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>lockedInterfaceDefinition</spirit:name>
<spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>systemInfos</spirit:name>
<spirit:displayName>systemInfos</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
<connPtSystemInfos/>
</systemInfosDefinition>]]></spirit:value>
</spirit:parameter>
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
<altera:interface_mapping altera:name="complex_input" altera:internal="altmult_complex_0.complex_input" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="aclr" altera:internal="aclr"></altera:port_mapping>
<altera:port_mapping altera:name="clock" altera:internal="clock"></altera:port_mapping>
<altera:port_mapping altera:name="dataa_imag" altera:internal="dataa_imag"></altera:port_mapping>
<altera:port_mapping altera:name="dataa_real" altera:internal="dataa_real"></altera:port_mapping>
<altera:port_mapping altera:name="datab_imag" altera:internal="datab_imag"></altera:port_mapping>
<altera:port_mapping altera:name="datab_real" altera:internal="datab_real"></altera:port_mapping>
<altera:port_mapping altera:name="ena" altera:internal="ena"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="complex_output" altera:internal="altmult_complex_0.complex_output" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="result_imag" altera:internal="result_imag"></altera:port_mapping>
<altera:port_mapping altera:name="result_real" altera:internal="result_real"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
<altera:altera_has_warnings>false</altera:altera_has_warnings>
<altera:altera_has_errors>false</altera:altera_has_errors>
</spirit:vendorExtensions>
</spirit:component>
\ No newline at end of file
libraries/technology/mult/tech_complex_mult.vhd
+ 12
− 12
View file @ 6504afb8
......@@ -227,18 +227,18 @@ BEGIN
br <= RESIZE_SVEC(in_br, c_dsp_mult_27_w);
bi <= RESIZE_SVEC(in_bi, c_dsp_mult_27_w) WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_27_w);
--u0 : ip_arria10_e1sg_complex_mult_27b
--PORT MAP (
-- aclr => rst,
-- clock => clk,
-- dataa_imag => ai,
-- dataa_real => ar,
-- datab_imag => bi,
-- datab_real => br,
-- ena => clken,
-- result_imag => mult_im,
-- result_real => mult_re
--);
u0 : ip_arria10_e1sg_complex_mult_27b
PORT MAP (
aclr => rst,
clock => clk,
dataa_imag => ai,
dataa_real => ar,
datab_imag => bi,
datab_real => br,
ena => clken,
result_imag => mult_im,
result_real => mult_re
);
-- Back to true input widths and then resize for output width
result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
......
libraries/technology/mult/tech_mult_component_pkg.vhd
+ 26
− 0
View file @ 6504afb8
......@@ -361,6 +361,19 @@ PACKAGE tech_mult_component_pkg IS
);
END COMPONENT;
COMPONENT ip_arria10_e1sg_complex_mult_27b is
PORT (
dataa_real : in std_logic_vector(26 downto 0) := (others => '0'); -- complex_input.dataa_real
dataa_imag : in std_logic_vector(26 downto 0) := (others => '0'); -- .dataa_imag
datab_real : in std_logic_vector(26 downto 0) := (others => '0'); -- .datab_real
datab_imag : in std_logic_vector(26 downto 0) := (others => '0'); -- .datab_imag
clock : in std_logic := '0'; -- .clk
aclr : in std_logic := '0'; -- .aclr
ena : in std_logic := '0'; -- .ena
result_real : out std_logic_vector(53 downto 0); -- complex_output.result_real
result_imag : out std_logic_vector(53 downto 0) -- .result_imag
);
END COMPONENT;
-----------------------------------------------------------------------------
-- Arria 10 e2sg components
-----------------------------------------------------------------------------
......@@ -426,4 +439,17 @@ PACKAGE tech_mult_component_pkg IS
);
END COMPONENT;
COMPONENT ip_arria10_e2sg_complex_mult_27b is
PORT (
dataa_real : in std_logic_vector(26 downto 0) := (others => '0'); -- complex_input.dataa_real
dataa_imag : in std_logic_vector(26 downto 0) := (others => '0'); -- .dataa_imag
datab_real : in std_logic_vector(26 downto 0) := (others => '0'); -- .datab_real
datab_imag : in std_logic_vector(26 downto 0) := (others => '0'); -- .datab_imag
clock : in std_logic := '0'; -- .clk
aclr : in std_logic := '0'; -- .aclr
ena : in std_logic := '0'; -- .ena
result_real : out std_logic_vector(53 downto 0); -- complex_output.result_real
result_imag : out std_logic_vector(53 downto 0) -- .result_imag
);
END COMPONENT;
END tech_mult_component_pkg;
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