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hdllib.cfg 565 B 
hdl_lib_name = ip_agi027_xxxx_ram
hdl_library_clause_name = ip_agi027_xxxx_ram_lib
hdl_lib_uses_synth = technology
hdl_lib_uses_sim = 
hdl_lib_technology = ip_agi027_xxxx

synth_files =
    ip_agi027_xxxx_true_dual_port_ram_single_clock.vhd
    ip_agi027_xxxx_simple_dual_port_ram_dual_clock.vhd
    ip_agi027_xxxx_simple_dual_port_ram_single_clock.vhd
    
    ip_agi027_xxxx_ram_cr_cw.vhd
    ip_agi027_xxxx_ram_crk_cw.vhd
    ip_agi027_xxxx_ram_rw_rw.vhd
    ip_agi027_xxxx_ram_r_w.vhd
    
test_bench_files =


[modelsim_project_file]


[quartus_project_file]