dp_latency_fifo.vhd

-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------

LIBRARY IEEE, common_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE work.dp_stream_pkg.ALL;

-- Purpose: Simple DP fifo in registers.
-- Description:
--   The fifo can store up to g_fifo_size words. When the FIFO is full then 
--   the snk_out.ready is '0', so wr_ful is equivalent and equal to NOT
--   snk_out.ready.
--
-- Remark:
-- . Uses a dp_latency_adapter as FIFO.
-- . Choose g_fifo_size > g_output_rl - g_input_rl to ensure that
--   c_adapter_input_rl > c_adapter_output_rl, because only then the FIFO
--   logic will be instantiated inside the dp_latency_adapter 

ENTITY dp_latency_fifo IS
  GENERIC (
    g_bypass       : BOOLEAN := FALSE;  -- for clarity rather use g_bypass=TRUE than equivalent g_fifo_size=0
    g_input_rl     : NATURAL := 1;      -- input ready latency
    g_output_rl    : NATURAL := 1;      -- output ready latency
    g_fifo_size    : NATURAL := 1       -- must be g_fifo_size > g_output_rl - g_input_rl
  );
  PORT (
    rst          : IN  STD_LOGIC;
    clk          : IN  STD_LOGIC;
    -- Monitor FIFO filling
    usedw        : OUT STD_LOGIC_VECTOR(ceil_log2(2+g_input_rl+g_fifo_size)-1 DOWNTO 0);  -- +3 to match dp_latency_adapter usedw width
    wr_ful       : OUT STD_LOGIC;
    rd_emp       : OUT STD_LOGIC;
    -- ST sink
    snk_out      : OUT t_dp_siso;
    snk_in       : IN  t_dp_sosi;
    -- ST source
    src_in       : IN  t_dp_siso;
    src_out      : OUT t_dp_sosi
  );
END dp_latency_fifo;


ARCHITECTURE rtl OF dp_latency_fifo IS
  
  CONSTANT c_adapter_input_rl  : NATURAL := g_input_rl + g_fifo_size;
  CONSTANT c_adapter_output_rl : NATURAL := g_output_rl;
    
  SIGNAL i_snk_out    : t_dp_siso;
  SIGNAL fifo_snk_out : t_dp_siso;
  SIGNAL i_usedw      : STD_LOGIC_VECTOR(usedw'RANGE);
  
BEGIN

  gen_bypass : IF g_bypass=TRUE GENERATE
    snk_out <= src_in;
    src_out <= snk_in;
  END GENERATE;
  
  no_bypass : IF g_bypass=FALSE GENERATE

    snk_out <= i_snk_out;
    usedw   <= i_usedw;
    
    -- pass on frame level flow control
    i_snk_out.xon <= src_in.xon;
    
    -- pass on sample level flow control similar as in dp_latency_adapter but now with extra margin of g_fifo_size
    p_snk_out_ready : PROCESS(i_usedw, fifo_snk_out, snk_in)      -- equivalent to p_snk_out_ready in dp_latency_adapter
    BEGIN
      i_snk_out.ready <= '0';
      IF fifo_snk_out.ready='1' THEN                              -- equivalent to ff_siso.ready in dp_latency_adapter
        -- Default snk_out ready when the source is ready.
        i_snk_out.ready <= '1';
      ELSE
        -- Extra snk_out ready to look ahead for fifo_snk_out RL = 0 and to fill the FIFO.
        IF TO_UINT(i_usedw) < c_adapter_input_rl THEN                -- equivalent to fifo_reg(0).valid='0' in dp_latency_adapter
          i_snk_out.ready <= '1';
        ELSIF TO_UINT(i_usedw) = c_adapter_input_rl THEN             -- equivalent to fifo_reg(1).valid='0' in dp_latency_adapter
          i_snk_out.ready <= NOT(snk_in.valid);
        END IF;
      END IF;
    END PROCESS;
    
    -- define FIFO full as not ready for new input    
    wr_ful <= NOT i_snk_out.ready;
    
    u_dp_latency_adapter : ENTITY work.dp_latency_adapter
    GENERIC MAP (
      g_in_latency  => c_adapter_input_rl,
      g_out_latency => c_adapter_output_rl
    )
    PORT MAP (
      rst          => rst,
      clk          => clk,
      -- Monitor internal FIFO filling
      fifo_usedw   => i_usedw,
      fifo_ful     => OPEN,
      fifo_emp     => rd_emp,
      -- ST sink
      snk_out      => fifo_snk_out,
      snk_in       => snk_in,
      -- ST source
      src_in       => src_in,
      src_out      => src_out
    );
  END GENERATE;
    
END rtl;