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Commit 3a59e0a9 authored by Eric Kooistra's avatar Eric Kooistra
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Added g_input_rl and g_output_rl which can be >= 0.

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libraries/base/dp/src/vhdl/dp_latency_fifo.vhd
+ 14
− 7
View file @ 3a59e0a9
......@@ -32,19 +32,23 @@ USE work.dp_stream_pkg.ALL;
-- snk_out.ready.
--
-- Remark:
-- . Fixed RL = 1
-- . Uses a dp_latency_adapter as FIFO.
-- . Choose g_fifo_size > g_output_rl - g_input_rl to ensure that
-- c_adapter_input_rl > c_adapter_output_rl, because only then the FIFO
-- logic will be instantiated inside the dp_latency_adapter
ENTITY dp_latency_fifo IS
GENERIC (
g_bypass : BOOLEAN := FALSE; -- for clarity rather use g_bypass=TRUE than equivalent g_fifo_size=0
g_fifo_size : NATURAL := 1
g_input_rl : NATURAL := 1; -- input ready latency
g_output_rl : NATURAL := 1; -- output ready latency
g_fifo_size : NATURAL := 1 -- must be g_fifo_size > g_output_rl - g_input_rl
);
PORT (
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
-- Monitor FIFO filling
usedw : OUT STD_LOGIC_VECTOR(ceil_log2(3+g_fifo_size)-1 DOWNTO 0); -- +3 to match dp_latency_adapter usedw width
usedw : OUT STD_LOGIC_VECTOR(ceil_log2(2+g_input_rl+g_fifo_size)-1 DOWNTO 0); -- +3 to match dp_latency_adapter usedw width
wr_ful : OUT STD_LOGIC;
rd_emp : OUT STD_LOGIC;
-- ST sink
......@@ -59,6 +63,9 @@ END dp_latency_fifo;
ARCHITECTURE rtl OF dp_latency_fifo IS
CONSTANT c_adapter_input_rl : NATURAL := g_input_rl + g_fifo_size;
CONSTANT c_adapter_output_rl : NATURAL := g_output_rl;
SIGNAL i_snk_out : t_dp_siso;
SIGNAL fifo_snk_out : t_dp_siso;
SIGNAL i_usedw : STD_LOGIC_VECTOR(usedw'RANGE);
......@@ -87,9 +94,9 @@ BEGIN
i_snk_out.ready <= '1';
ELSE
-- Extra snk_out ready to look ahead for fifo_snk_out RL = 0 and to fill the FIFO.
IF TO_UINT(i_usedw) < 1 + g_fifo_size THEN -- equivalent to fifo_reg(0).valid='0' in dp_latency_adapter
IF TO_UINT(i_usedw) < c_adapter_input_rl THEN -- equivalent to fifo_reg(0).valid='0' in dp_latency_adapter
i_snk_out.ready <= '1';
ELSIF TO_UINT(i_usedw) = 1 + g_fifo_size THEN -- equivalent to fifo_reg(1).valid='0' in dp_latency_adapter
ELSIF TO_UINT(i_usedw) = c_adapter_input_rl THEN -- equivalent to fifo_reg(1).valid='0' in dp_latency_adapter
i_snk_out.ready <= NOT(snk_in.valid);
END IF;
END IF;
......@@ -100,8 +107,8 @@ BEGIN
u_dp_latency_adapter : ENTITY work.dp_latency_adapter
GENERIC MAP (
g_in_latency => 1+g_fifo_size,
g_out_latency => 1
g_in_latency => c_adapter_input_rl,
g_out_latency => c_adapter_output_rl
)
PORT MAP (
rst => rst,
......
libraries/base/dp/tb/vhdl/tb_dp_latency_fifo.vhd
+ 9
− 6
View file @ 3a59e0a9
......@@ -39,6 +39,8 @@ USE work.tb_dp_pkg.ALL;
ENTITY tb_dp_latency_fifo IS
GENERIC (
g_bypass : BOOLEAN := FALSE; -- for clarity rather use g_bypass=TRUE than equivalent g_fifo_size=0
g_input_rl : NATURAL := 1; -- input ready latency
g_output_rl : NATURAL := 1; -- output ready latency
g_fifo_size : NATURAL := 1;
g_nof_symbols_per_block : NATURAL := 51;
g_nof_symbols_per_data : NATURAL := 4;
......@@ -53,7 +55,6 @@ ARCHITECTURE tb OF tb_dp_latency_fifo IS
CONSTANT c_nof_data_per_block : NATURAL := ceil_div(g_nof_symbols_per_block, g_nof_symbols_per_data);
-- tb default
CONSTANT c_rl : NATURAL := 1;
CONSTANT c_pulse_0_active : NATURAL := c_nof_data_per_block;
CONSTANT c_pulse_0_gap : NATURAL := 10;
CONSTANT c_pulse_0_period : NATURAL := c_nof_data_per_block + c_pulse_0_gap;
......@@ -85,7 +86,7 @@ ARCHITECTURE tb OF tb_dp_latency_fifo IS
SIGNAL verify_en : STD_LOGIC := '0';
SIGNAL verify_done : STD_LOGIC := '0';
SIGNAL prev_out_ready : STD_LOGIC_VECTOR(0 TO c_rl);
SIGNAL prev_out_ready : STD_LOGIC_VECTOR(0 TO g_output_rl);
SIGNAL prev_out_data : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
SIGNAL expected_out_data : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
......@@ -99,7 +100,7 @@ ARCHITECTURE tb OF tb_dp_latency_fifo IS
SIGNAL in_sop : STD_LOGIC;
SIGNAL in_eop : STD_LOGIC;
SIGNAL fifo_usedw : STD_LOGIC_VECTOR(ceil_log2(3+g_fifo_size)-1 DOWNTO 0); -- +3 to match dp_latency_fifo usedw width
SIGNAL fifo_usedw : STD_LOGIC_VECTOR(ceil_log2(2+g_input_rl+g_fifo_size)-1 DOWNTO 0); -- +2+g_input_rl to match dp_latency_fifo usedw width
SIGNAL fifo_ful : STD_LOGIC;
SIGNAL fifo_emp : STD_LOGIC;
......@@ -155,7 +156,7 @@ BEGIN
-- Begin of stimuli
FOR R IN 0 TO c_nof_repeat-1 LOOP
proc_dp_gen_block_data(c_rl, TRUE, c_data_w, c_symbol_w, v_symbol, 0, 0, g_nof_symbols_per_block, v_channel, v_err, v_sync, v_bsn, clk, in_en, in_siso, in_sosi);
proc_dp_gen_block_data(g_input_rl, TRUE, c_data_w, c_symbol_w, v_symbol, 0, 0, g_nof_symbols_per_block, v_channel, v_err, v_sync, v_bsn, clk, in_en, in_siso, in_sosi);
v_bsn := INCR_UVEC(v_bsn, 1);
v_symbol := (v_symbol + g_nof_symbols_per_block) MOD c_symbol_mod;
v_channel := v_channel + 1;
......@@ -183,12 +184,12 @@ BEGIN
verify_en <= '1' WHEN rising_edge(clk) AND out_sosi.sop='1'; -- verify enable after first output sop
-- SOSI control
proc_dp_verify_valid(c_rl, clk, verify_en, out_siso.ready, prev_out_ready, out_val); -- Verify that the output valid fits with the output ready latency
proc_dp_verify_valid(g_output_rl, clk, verify_en, out_siso.ready, prev_out_ready, out_val); -- Verify that the output valid fits with the output ready latency
proc_dp_verify_gap_invalid(clk, out_val, out_sop, out_eop, out_gap); -- Verify that the output valid is low between blocks from eop to sop
-- SOSI data
-- . verify that the output is incrementing symbols, like the input stimuli
proc_dp_verify_symbols(c_rl, c_data_w, c_symbol_w, clk, verify_en, out_siso.ready, out_sosi.valid, out_sosi.eop, out_data, out_sosi.empty, prev_out_data);
proc_dp_verify_symbols(g_output_rl, c_data_w, c_symbol_w, clk, verify_en, out_siso.ready, out_sosi.valid, out_sosi.eop, out_data, out_sosi.empty, prev_out_data);
-- . verify that the stimuli have been applied at all
proc_dp_verify_value(e_equal, clk, verify_done, expected_out_data, out_data);
......@@ -201,6 +202,8 @@ BEGIN
dut : ENTITY work.dp_latency_fifo
GENERIC MAP (
g_bypass => g_bypass,
g_input_rl => g_input_rl, -- input ready latency
g_output_rl => g_output_rl, -- output ready latency
g_fifo_size => g_fifo_size
)
PORT MAP (
......
libraries/base/dp/tb/vhdl/tb_tb_dp_latency_fifo.vhd
+ 18
− 9
View file @ 3a59e0a9
......@@ -37,22 +37,31 @@ BEGIN
-- > run -all --> OK
-- g_bypass : BOOLEAN := FALSE; -- for clarity rather use g_bypass=TRUE than equivalent g_fifo_size=0
-- g_input_rl : NATURAL := 1; -- input ready latency
-- g_output_rl : NATURAL := 1; -- output ready latency
-- g_fifo_size : NATURAL := 1;
-- g_nof_symbols_per_block : NATURAL := 51;
-- g_nof_symbols_per_data : NATURAL := 4;
-- g_in_en : t_dp_flow_control_enum := e_active, e_random or e_pulse flow control
-- g_out_ready : t_dp_flow_control_enum := e_active, e_random or e_pulse flow control
u_fifo_bypass : ENTITY work.tb_dp_latency_fifo GENERIC MAP (TRUE, 1, 51, 4, e_active, e_active);
u_fifo_0 : ENTITY work.tb_dp_latency_fifo GENERIC MAP (FALSE, 0, 51, 4, e_active, e_active); -- try bypass via g_fifo_size=0
u_fifo_bypass : ENTITY work.tb_dp_latency_fifo GENERIC MAP (TRUE, 1, 1, 1, 51, 4, e_active, e_active);
u_fifo_0 : ENTITY work.tb_dp_latency_fifo GENERIC MAP (FALSE, 1, 1, 0, 51, 4, e_active, e_active); -- try bypass via g_fifo_size=0
u_fifo_1_act_act : ENTITY work.tb_dp_latency_fifo GENERIC MAP (FALSE, 1, 51, 4, e_active, e_active);
u_fifo_1_rnd_act : ENTITY work.tb_dp_latency_fifo GENERIC MAP (FALSE, 1, 51, 4, e_random, e_active);
u_fifo_1_rnd_rnd : ENTITY work.tb_dp_latency_fifo GENERIC MAP (FALSE, 1, 51, 4, e_random, e_random);
u_fifo_1_pls_rnd : ENTITY work.tb_dp_latency_fifo GENERIC MAP (FALSE, 1, 51, 4, e_pulse, e_random);
u_fifo_1_act_act : ENTITY work.tb_dp_latency_fifo GENERIC MAP (FALSE, 1, 1, 1, 51, 4, e_active, e_active);
u_fifo_1_rnd_act : ENTITY work.tb_dp_latency_fifo GENERIC MAP (FALSE, 1, 1, 1, 51, 4, e_random, e_active);
u_fifo_1_rnd_rnd : ENTITY work.tb_dp_latency_fifo GENERIC MAP (FALSE, 1, 1, 1, 51, 4, e_random, e_random);
u_fifo_1_pls_rnd : ENTITY work.tb_dp_latency_fifo GENERIC MAP (FALSE, 1, 1, 1, 51, 4, e_pulse, e_random);
u_fifo_2_rnd_rnd : ENTITY work.tb_dp_latency_fifo GENERIC MAP (FALSE, 2, 51, 4, e_random, e_random);
u_fifo_2_pls_rnd : ENTITY work.tb_dp_latency_fifo GENERIC MAP (FALSE, 2, 51, 4, e_pulse, e_random);
u_fifo_3_pls_rnd : ENTITY work.tb_dp_latency_fifo GENERIC MAP (FALSE, 3, 51, 4, e_pulse, e_random);
u_fifo_1_act_act_rl_0_0 : ENTITY work.tb_dp_latency_fifo GENERIC MAP (FALSE, 0, 0, 1, 51, 4, e_active, e_active);
u_fifo_1_act_act_rl_0_1 : ENTITY work.tb_dp_latency_fifo GENERIC MAP (FALSE, 0, 1, 2, 51, 4, e_active, e_active);
u_fifo_1_act_act_rl_1_0 : ENTITY work.tb_dp_latency_fifo GENERIC MAP (FALSE, 1, 0, 1, 51, 4, e_active, e_active);
u_fifo_1_rnd_rnd_rl_0_0 : ENTITY work.tb_dp_latency_fifo GENERIC MAP (FALSE, 0, 0, 1, 51, 4, e_random, e_random);
u_fifo_1_rnd_rnd_rl_0_1 : ENTITY work.tb_dp_latency_fifo GENERIC MAP (FALSE, 0, 1, 2, 51, 4, e_random, e_random);
u_fifo_1_rnd_rnd_rl_1_0 : ENTITY work.tb_dp_latency_fifo GENERIC MAP (FALSE, 1, 0, 1, 51, 4, e_random, e_random);
u_fifo_2_rnd_rnd : ENTITY work.tb_dp_latency_fifo GENERIC MAP (FALSE, 1, 1, 2, 51, 4, e_random, e_random);
u_fifo_2_pls_rnd : ENTITY work.tb_dp_latency_fifo GENERIC MAP (FALSE, 1, 1, 2, 51, 4, e_pulse, e_random);
u_fifo_3_pls_rnd : ENTITY work.tb_dp_latency_fifo GENERIC MAP (FALSE, 1, 1, 3, 51, 4, e_pulse, e_random);
END tb;
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