dp_fifo_to_mm.vhd

-------------------------------------------------------------------------------
--
-- Copyright (C) 2011
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------

LIBRARY IEEE, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE work.dp_stream_pkg.ALL;

-- Purpose:
--   Provide MM access to the ST output of a FIFO.
-- Description:
--   An MM master can directly read the FIFO, provided that the ST data width
--   fits within the MM data width (g_mm_word_w) and that both have the same
--   latency (read latency = ready latency = 1).
--   The MM master can read the mm_usedw[] value to know how many valid data
--   words it can read in a loop, until it needs to check mm_usedw[] again.
--   When mm_usedw[] > 0 then the MM master can be sure that the read
--   mm_rddata will be valid. Therefore it is not needed to pass on
--   snk_in.valid and in this way the MM master does not need to check whether
--   there is valid data in the FIFO for every read fifo data access.
-- Remark:
-- . Assume the FIFO will never go completely full, so usedw[] only needs to 
--   fit values <= g_fifo_size-1
-- . This dp_fifo_to_mm connects to the MM clock domain side of the FIFO, hence
--   is operates entirely in the MM clock domain.
-- . The ST sop, eop, empty, channel and error fields are not supported.


ENTITY dp_fifo_to_mm IS
  GENERIC (
    g_fifo_size   : NATURAL := 512;
    g_mm_word_w   : NATURAL := c_word_w     -- = 32
  );
  PORT (
    rst           : IN  STD_LOGIC;    -- MM clock domain
    clk           : IN  STD_LOGIC;
    -- ST sink connected to FIFO output
    snk_out       : OUT t_dp_siso;
    snk_in        : IN  t_dp_sosi;
    usedw         : IN  STD_LOGIC_VECTOR(ceil_log2(g_fifo_size)-1 DOWNTO 0);
    -- Control for FIFO read access
    mm_rd         : IN  STD_LOGIC;    -- MM read pulse to read the mm_rddata from snk_in.data
    mm_rddata     : OUT STD_LOGIC_VECTOR(g_mm_word_w-1 DOWNTO 0);
    mm_rdval      : OUT STD_LOGIC;
    mm_usedw      : OUT STD_LOGIC_VECTOR(g_mm_word_w-1 DOWNTO 0)
  );
END dp_fifo_to_mm;


ARCHITECTURE str OF dp_fifo_to_mm IS

BEGIN

  -- Wires
  mm_usedw <= RESIZE_UVEC(usedw, g_mm_word_w);

  -- XON fixed to '1' after reset
  snk_out.xon <= NOT rst;
                                                      
  snk_out.ready <= mm_rd;  -- Combinatorial, because FIFO RL=1 already fits MM read latency=1
  mm_rddata     <= RESIZE_UVEC(snk_in.data, g_mm_word_w);
  mm_rdval      <= snk_in.valid;

END str;