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tech_ddr_mem_model.vhd

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    tech_ddr_mem_model.vhd 6.92 KiB
    --------------------------------------------------------------------------------
    --
    -- Copyright (C) 2014
    -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
    -- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
    -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
    --
    -- This program is free software: you can redistribute it and/or modify
    -- it under the terms of the GNU General Public License as published by
    -- the Free Software Foundation, either version 3 of the License, or
    -- (at your option) any later version.
    --
    -- This program is distributed in the hope that it will be useful,
    -- but WITHOUT ANY WARRANTY; without even the implied warranty of
    -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    -- GNU General Public License for more details.
    --
    -- You should have received a copy of the GNU General Public License
    -- along with this program.  If not, see <http://www.gnu.org/licenses/>.
    --
    --------------------------------------------------------------------------------
    
    -- Purpose: DDR3 or DDR4 memory model for simulation.
    -- Description:
    --   Dependent on g_tech_ddr.name either a DDR3 memory or a DDR4 memory model
    --   gets instantiated.
    --   If DDR3 is selected then the mem4 ports remain unused.
    --   If DDR4 is selected then the mem3 ports remain unused.
    --   The DDR3 memory model is not FPGA specific, but it was created by the example design for ip_stratixiv_ddr3_uphy_4g_800_master.
    --   Therefore the ip_stratixiv_ddr3_uphy_4g_800_master_lib is needed if the model is used.
    
    -- Declare IP libraries to ensure default binding in simulation.
    LIBRARY ip_stratixiv_ddr3_mem_model_lib;
    LIBRARY ed_sim_altera_emif_mem_model_core_ddr4_141;
    
    
    LIBRARY IEEE, common_lib;
    USE IEEE.STD_LOGIC_1164.ALL;
    USE common_lib.common_pkg.ALL;
    USE work.tech_ddr_pkg.ALL;
    USE work.tech_ddr_mem_model_component_pkg.ALL;
    
    ENTITY tech_ddr_memory_model IS
      GENERIC (
        g_tech_ddr   : t_c_tech_ddr
      );
      PORT (
        -- DDR3 PHY interface
        mem3_in       : IN    t_tech_ddr3_phy_ou := c_tech_ddr3_phy_ou_x;
        mem3_io       : INOUT t_tech_ddr3_phy_io;
        mem3_ou       : OUT   t_tech_ddr3_phy_in;
        -- DDR4 PHY interface
        mem4_in       : IN    t_tech_ddr4_phy_ou := c_tech_ddr4_phy_ou_x;
        mem4_io       : INOUT t_tech_ddr4_phy_io;
        mem4_ou       : OUT   t_tech_ddr4_phy_in
      );
    END tech_ddr_memory_model;
    
    
    ARCHITECTURE str OF tech_ddr_memory_model IS
    
      CONSTANT c_gigabytes    : NATURAL := func_tech_ddr_module_size(g_tech_ddr);
    
      SIGNAL dbg_g_tech_ddr   : t_c_tech_ddr := g_tech_ddr;
      SIGNAL dbg_c_gigabytes  : NATURAL := c_gigabytes;
      
    BEGIN
    
      gen_ip_stratixiv_ddr_memory_model : IF g_tech_ddr.name="DDR3" GENERATE
        u_ip_stratixiv_ddr_memory_model : alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en