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Corné Lukken
sdptr
Commits
995bf1c7
Commit
995bf1c7
authored
Sep 2, 2021
by
Pieter Donker
Browse files
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Plain Diff
L2SDP-354
, proccess review comment in wrong branch
parent
be89aa98
No related branches found
No related tags found
No related merge requests found
Changes
5
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5 changed files
src/fpga.cpp
+12
-14
12 additions, 14 deletions
src/fpga.cpp
src/fpga.h
+2
-2
2 additions, 2 deletions
src/fpga.h
src/node.cpp
+3
-3
3 additions, 3 deletions
src/node.cpp
src/node.h
+2
-2
2 additions, 2 deletions
src/node.h
src/periph/fpga.cpp
+0
-40
0 additions, 40 deletions
src/periph/fpga.cpp
with
19 additions
and
61 deletions
src/fpga.cpp
+
12
−
14
View file @
995bf1c7
...
...
@@ -46,8 +46,8 @@ using namespace std;
extern
int
debug
;
Fpga
::
Fpga
(
list
<
class
Node
*>&
nodelist
,
const
int32_t
n_beam
_
sets
)
:
n
_b
eamsets
(
n_beam
_
sets
),
Fpga
::
Fpga
(
list
<
class
Node
*>&
nodelist
,
const
int32_t
n_beamsets
)
:
n
B
eamsets
(
n_beamsets
),
FPGA
(
nodelist
)
{
pointMap
=
new
CPointMap
();
...
...
@@ -72,16 +72,14 @@ Fpga::Fpga(list<class Node*>& nodelist, const int32_t n_beam_sets):
pointMap
->
add_register
(
"FPGA_sst_offload_hdr_udp_destination_port_R"
,
"fpga/sst_offload_hdr_udp_destination_port"
,
nodes
.
size
(),
1
,
"RO"
,
REG_FORMAT_UINT16
);
pointMap
->
add_register
(
"FPGA_sst_offload_hdr_udp_destination_port_RW"
,
"fpga/sst_offload_hdr_udp_destination_port"
,
nodes
.
size
(),
1
,
"RW"
,
REG_FORMAT_UINT16
);
pointMap
->
add_register
(
"FPGA_bst_offload_enable_R"
,
"fpga/bst_offload_enable"
,
nodes
.
size
(),
n_beamsets
,
"RO"
,
REG_FORMAT_BOOLEAN
);
pointMap
->
add_register
(
"FPGA_bst_offload_enable_RW"
,
"fpga/bst_offload_enable"
,
nodes
.
size
(),
n_beamsets
,
"RW"
,
REG_FORMAT_BOOLEAN
);
pointMap
->
add_register
(
"FPGA_bst_offload_hdr_eth_destination_mac_R"
,
"fpga/bst_offload_hdr_eth_destination_mac"
,
nodes
.
size
(),
n_beamsets
,
"RO"
,
REG_FORMAT_STRING
);
pointMap
->
add_register
(
"FPGA_bst_offload_hdr_eth_destination_mac_RW"
,
"fpga/bst_offload_hdr_eth_destination_mac"
,
nodes
.
size
(),
n_beamsets
,
"RW"
,
REG_FORMAT_STRING
);
pointMap
->
add_register
(
"FPGA_bst_offload_hdr_ip_destination_address_R"
,
"fpga/bst_offload_hdr_ip_destination_address"
,
nodes
.
size
(),
n_beamsets
,
"RO"
,
REG_FORMAT_STRING
);
pointMap
->
add_register
(
"FPGA_bst_offload_hdr_ip_destination_address_RW"
,
"fpga/bst_offload_hdr_ip_destination_address"
,
nodes
.
size
(),
n_beamsets
,
"RW"
,
REG_FORMAT_STRING
);
pointMap
->
add_register
(
"FPGA_bst_offload_hdr_udp_destination_port_R"
,
"fpga/bst_offload_hdr_udp_destination_port"
,
nodes
.
size
(),
n_beamsets
,
"RO"
,
REG_FORMAT_UINT16
);
pointMap
->
add_register
(
"FPGA_bst_offload_hdr_udp_destination_port_RW"
,
"fpga/bst_offload_hdr_udp_destination_port"
,
nodes
.
size
(),
n_beamsets
,
"RW"
,
REG_FORMAT_UINT16
);
// pointMap->add_register("FPGA_bst_offload_nof_beamlets_per_packet_R", "fpga/bst_offload_nof_beamlets_per_packet", nodes.size(), n_beamsets, "RO", REG_FORMAT_UINT32);
// pointMap->add_register("FPGA_bst_offload_nof_beamlets_per_packet_RW", "fpga/bst_offload_nof_beamlets_per_packet", nodes.size(), n_beamsets, "RW", REG_FORMAT_UINT32);
pointMap
->
add_register
(
"FPGA_bst_offload_enable_R"
,
"fpga/bst_offload_enable"
,
nodes
.
size
(),
nBeamsets
,
"RO"
,
REG_FORMAT_BOOLEAN
);
pointMap
->
add_register
(
"FPGA_bst_offload_enable_RW"
,
"fpga/bst_offload_enable"
,
nodes
.
size
(),
nBeamsets
,
"RW"
,
REG_FORMAT_BOOLEAN
);
pointMap
->
add_register
(
"FPGA_bst_offload_hdr_eth_destination_mac_R"
,
"fpga/bst_offload_hdr_eth_destination_mac"
,
nodes
.
size
(),
nBeamsets
,
"RO"
,
REG_FORMAT_STRING
);
pointMap
->
add_register
(
"FPGA_bst_offload_hdr_eth_destination_mac_RW"
,
"fpga/bst_offload_hdr_eth_destination_mac"
,
nodes
.
size
(),
nBeamsets
,
"RW"
,
REG_FORMAT_STRING
);
pointMap
->
add_register
(
"FPGA_bst_offload_hdr_ip_destination_address_R"
,
"fpga/bst_offload_hdr_ip_destination_address"
,
nodes
.
size
(),
nBeamsets
,
"RO"
,
REG_FORMAT_STRING
);
pointMap
->
add_register
(
"FPGA_bst_offload_hdr_ip_destination_address_RW"
,
"fpga/bst_offload_hdr_ip_destination_address"
,
nodes
.
size
(),
nBeamsets
,
"RW"
,
REG_FORMAT_STRING
);
pointMap
->
add_register
(
"FPGA_bst_offload_hdr_udp_destination_port_R"
,
"fpga/bst_offload_hdr_udp_destination_port"
,
nodes
.
size
(),
nBeamsets
,
"RO"
,
REG_FORMAT_UINT16
);
pointMap
->
add_register
(
"FPGA_bst_offload_hdr_udp_destination_port_RW"
,
"fpga/bst_offload_hdr_udp_destination_port"
,
nodes
.
size
(),
nBeamsets
,
"RW"
,
REG_FORMAT_UINT16
);
pointMap
->
add_register
(
"FPGA_xst_subband_select_R"
,
"fpga/xst_subband_select"
,
nodes
.
size
(),
1
+
C_N_crosslets_max
,
"RO"
,
REG_FORMAT_UINT32
);
pointMap
->
add_register
(
"FPGA_xst_subband_select_RW"
,
"fpga/xst_subband_select"
,
nodes
.
size
(),
1
+
C_N_crosslets_max
,
"RW"
,
REG_FORMAT_UINT32
);
...
...
@@ -141,8 +139,8 @@ Fpga::Fpga(list<class Node*>& nodelist, const int32_t n_beam_sets):
pointMap
->
add_register
(
"FPGA_scrap_R"
,
"fpga/scrap"
,
nodes
.
size
(),
C_N_scrap
,
"RO"
,
REG_FORMAT_UINT32
);
pointMap
->
add_register
(
"FPGA_scrap_RW"
,
"fpga/scrap"
,
nodes
.
size
(),
C_N_scrap
,
"RW"
,
REG_FORMAT_UINT32
);
pointMap
->
add_register
(
"FPGA_weights_R"
,
"fpga/weights"
,
nodes
.
size
(),
C_S_pn
*
n
_b
eamsets
,
"RO"
,
REG_FORMAT_INT16
);
pointMap
->
add_register
(
"FPGA_weights_RW"
,
"fpga/weights"
,
nodes
.
size
(),
C_S_pn
*
n
_b
eamsets
,
"RW"
,
REG_FORMAT_INT16
);
pointMap
->
add_register
(
"FPGA_weights_R"
,
"fpga/weights"
,
nodes
.
size
(),
C_S_pn
*
n
B
eamsets
,
"RO"
,
REG_FORMAT_INT16
);
pointMap
->
add_register
(
"FPGA_weights_RW"
,
"fpga/weights"
,
nodes
.
size
(),
C_S_pn
*
n
B
eamsets
,
"RW"
,
REG_FORMAT_INT16
);
}
Fpga
::~
Fpga
()
...
...
This diff is collapsed.
Click to expand it.
src/fpga.h
+
2
−
2
View file @
995bf1c7
...
...
@@ -41,12 +41,12 @@
class
Fpga
{
private:
int32_t
n
_b
eamsets
;
int32_t
n
B
eamsets
;
std
::
list
<
class
Node
*>
FPGA
;
CPointMap
*
pointMap
;
public:
Fpga
(
std
::
list
<
class
Node
*>&
nodelist
,
const
int32_t
n_beam
_
sets
);
Fpga
(
std
::
list
<
class
Node
*>&
nodelist
,
const
int32_t
n_beamsets
);
~
Fpga
();
bool
point
(
TermOutput
&
termout
,
const
char
cmd
,
const
std
::
string
addr
,
...
...
This diff is collapsed.
Click to expand it.
src/node.cpp
+
3
−
3
View file @
995bf1c7
...
...
@@ -150,12 +150,12 @@ void Node::worker()
// << " leaving!!" << endl;
}
Node
::
Node
(
const
string
ipaddr
,
const
uint
unb
,
const
uint
localnr
,
const
string
type
,
const
uint
n_beamsets
)
:
Node
::
Node
(
const
string
ipaddr
,
const
uint
unb
,
const
uint
localnr
,
const
string
type
,
const
uint
n
of
_beamsets
)
:
myIPaddr
(
ipaddr
),
UniboardNr
(
unb
),
LocalNr
(
localnr
),
GlobalNr
(
localnr
+
4
*
unb
),
n
B
eamsets
(
n_beamsets
)
GlobalNr
(
localnr
+
FPGAS_PER_BOARD
*
unb
),
n
_b
eamsets
(
n
of
_beamsets
)
{
periph_fpga
=
new
Periph_fpga
(
GlobalNr
,
ipaddr
,
n_beamsets
);
...
...
This diff is collapsed.
Click to expand it.
src/node.h
+
2
−
2
View file @
995bf1c7
...
...
@@ -101,7 +101,7 @@ class Node {
uint
UniboardNr
;
uint
LocalNr
;
uint
GlobalNr
;
uint
n
B
eamsets
;
uint
n
_b
eamsets
;
std
::
string
Type
;
std
::
thread
*
worker_thread
;
...
...
@@ -116,7 +116,7 @@ class Node {
}
public
:
Node
(
const
std
::
string
ipaddr
,
const
uint
unb
,
const
uint
localnr
,
const
std
::
string
type
,
const
uint
n_beamsets
);
Node
(
const
std
::
string
ipaddr
,
const
uint
unb
,
const
uint
localnr
,
const
std
::
string
type
,
const
uint
n
of
_beamsets
);
~
Node
();
uint
ipaddr_to_id
(
const
std
::
string
ipaddr
);
...
...
This diff is collapsed.
Click to expand it.
src/periph/fpga.cpp
+
0
−
40
View file @
995bf1c7
...
...
@@ -207,9 +207,6 @@ bool Periph_fpga::read(TermOutput& termout, const string addr,
else
if
(
addr
==
"fpga/bst_offload_hdr_udp_destination_port"
)
{
retval
=
read_bst_offload_hdr_udp_destination_port
(
termout
,
format
);
}
else
if
(
addr
==
"fpga/bst_offload_nof_beamlets_per_packet"
)
{
retval
=
read_bst_offload_nof_beamlets_per_packet
(
termout
,
format
);
}
else
if
(
addr
==
"fpga/xst_offload_enable"
)
{
retval
=
read_xst_offload_enable
(
termout
,
format
);
}
...
...
@@ -408,9 +405,6 @@ bool Periph_fpga::write(TermOutput& termout, const string addr, const string typ
else
if
(
addr
==
"fpga/bst_offload_hdr_udp_destination_port"
)
{
retval
=
write_bst_offload_hdr_udp_destination_port
(
data
);
}
else
if
(
addr
==
"fpga/bst_offload_nof_beamlets_per_packet"
)
{
retval
=
write_bst_offload_nof_beamlets_per_packet
(
data
);
}
else
if
(
addr
==
"fpga/xst_offload_enable"
)
{
retval
=
write_xst_offload_enable
(
data
);
}
...
...
@@ -1379,40 +1373,6 @@ bool Periph_fpga::write_bst_offload_hdr_udp_destination_port(const char *data)
return
retval
;
}
bool
Periph_fpga
::
read_bst_offload_nof_beamlets_per_packet
(
TermOutput
&
termout
,
int
format
)
{
bool
retval
=
true
;
string
regname
;
uint32_t
data
[
20
];
int
*
_ptr
=
(
int
*
)
termout
.
val
;
for
(
uint32_t
i
=
0
;
i
<
nBeamsets
;
i
++
)
{
memset
((
void
*
)
data
,
0
,
sizeof
(
data
));
regname
=
"mm/"
+
to_string
(
i
)
+
"/REG_STAT_HDR_DAT_BST/0/TODO"
;
retval
&=
Read
(
regname
,
data
);
int
packets
=
(
int
)
data
[
i
];
*
_ptr
=
packets
;
_ptr
++
;
}
termout
.
nof_vals
=
nBeamsets
;
termout
.
datatype
=
format
;
return
retval
;
}
bool
Periph_fpga
::
write_bst_offload_nof_beamlets_per_packet
(
const
char
*
data
)
{
uint32_t
*
_ptr
=
(
uint32_t
*
)
data
;
bool
retval
=
true
;
string
regname
;
for
(
uint32_t
i
=
0
;
i
<
nBeamsets
;
i
++
)
{
regname
=
"mm/"
+
to_string
(
i
)
+
"/REG_STAT_HDR_DAT_BST/0/TODO"
;
if
(
Write
(
regname
,
&
_ptr
[
i
])
==
false
)
{
retval
=
false
;
}
}
return
retval
;
}
bool
Periph_fpga
::
read_xst_offload_enable
(
TermOutput
&
termout
,
int
format
)
{
bool
retval
=
true
;
...
...
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Click to expand it.
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