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Commit 995bf1c7 authored by Pieter Donker's avatar Pieter Donker
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L2SDP-354, proccess review comment in wrong branch

parent be89aa98
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......@@ -46,8 +46,8 @@ using namespace std;
extern int debug;
Fpga::Fpga(list<class Node*>& nodelist, const int32_t n_beam_sets):
n_beamsets(n_beam_sets),
Fpga::Fpga(list<class Node*>& nodelist, const int32_t n_beamsets):
nBeamsets(n_beamsets),
FPGA(nodelist)
{
pointMap = new CPointMap();
......@@ -72,16 +72,14 @@ Fpga::Fpga(list<class Node*>& nodelist, const int32_t n_beam_sets):
pointMap->add_register("FPGA_sst_offload_hdr_udp_destination_port_R", "fpga/sst_offload_hdr_udp_destination_port", nodes.size(), 1, "RO", REG_FORMAT_UINT16);
pointMap->add_register("FPGA_sst_offload_hdr_udp_destination_port_RW", "fpga/sst_offload_hdr_udp_destination_port", nodes.size(), 1, "RW", REG_FORMAT_UINT16);
pointMap->add_register("FPGA_bst_offload_enable_R", "fpga/bst_offload_enable", nodes.size(), n_beamsets, "RO", REG_FORMAT_BOOLEAN);
pointMap->add_register("FPGA_bst_offload_enable_RW", "fpga/bst_offload_enable", nodes.size(), n_beamsets, "RW", REG_FORMAT_BOOLEAN);
pointMap->add_register("FPGA_bst_offload_hdr_eth_destination_mac_R", "fpga/bst_offload_hdr_eth_destination_mac", nodes.size(), n_beamsets, "RO", REG_FORMAT_STRING);
pointMap->add_register("FPGA_bst_offload_hdr_eth_destination_mac_RW", "fpga/bst_offload_hdr_eth_destination_mac", nodes.size(), n_beamsets, "RW", REG_FORMAT_STRING);
pointMap->add_register("FPGA_bst_offload_hdr_ip_destination_address_R", "fpga/bst_offload_hdr_ip_destination_address", nodes.size(), n_beamsets, "RO", REG_FORMAT_STRING);
pointMap->add_register("FPGA_bst_offload_hdr_ip_destination_address_RW", "fpga/bst_offload_hdr_ip_destination_address", nodes.size(), n_beamsets, "RW", REG_FORMAT_STRING);
pointMap->add_register("FPGA_bst_offload_hdr_udp_destination_port_R", "fpga/bst_offload_hdr_udp_destination_port", nodes.size(), n_beamsets, "RO", REG_FORMAT_UINT16);
pointMap->add_register("FPGA_bst_offload_hdr_udp_destination_port_RW", "fpga/bst_offload_hdr_udp_destination_port", nodes.size(), n_beamsets, "RW", REG_FORMAT_UINT16);
// pointMap->add_register("FPGA_bst_offload_nof_beamlets_per_packet_R", "fpga/bst_offload_nof_beamlets_per_packet", nodes.size(), n_beamsets, "RO", REG_FORMAT_UINT32);
// pointMap->add_register("FPGA_bst_offload_nof_beamlets_per_packet_RW", "fpga/bst_offload_nof_beamlets_per_packet", nodes.size(), n_beamsets, "RW", REG_FORMAT_UINT32);
pointMap->add_register("FPGA_bst_offload_enable_R", "fpga/bst_offload_enable", nodes.size(), nBeamsets, "RO", REG_FORMAT_BOOLEAN);
pointMap->add_register("FPGA_bst_offload_enable_RW", "fpga/bst_offload_enable", nodes.size(), nBeamsets, "RW", REG_FORMAT_BOOLEAN);
pointMap->add_register("FPGA_bst_offload_hdr_eth_destination_mac_R", "fpga/bst_offload_hdr_eth_destination_mac", nodes.size(), nBeamsets, "RO", REG_FORMAT_STRING);
pointMap->add_register("FPGA_bst_offload_hdr_eth_destination_mac_RW", "fpga/bst_offload_hdr_eth_destination_mac", nodes.size(), nBeamsets, "RW", REG_FORMAT_STRING);
pointMap->add_register("FPGA_bst_offload_hdr_ip_destination_address_R", "fpga/bst_offload_hdr_ip_destination_address", nodes.size(), nBeamsets, "RO", REG_FORMAT_STRING);
pointMap->add_register("FPGA_bst_offload_hdr_ip_destination_address_RW", "fpga/bst_offload_hdr_ip_destination_address", nodes.size(), nBeamsets, "RW", REG_FORMAT_STRING);
pointMap->add_register("FPGA_bst_offload_hdr_udp_destination_port_R", "fpga/bst_offload_hdr_udp_destination_port", nodes.size(), nBeamsets, "RO", REG_FORMAT_UINT16);
pointMap->add_register("FPGA_bst_offload_hdr_udp_destination_port_RW", "fpga/bst_offload_hdr_udp_destination_port", nodes.size(), nBeamsets, "RW", REG_FORMAT_UINT16);
pointMap->add_register("FPGA_xst_subband_select_R", "fpga/xst_subband_select", nodes.size(), 1+C_N_crosslets_max, "RO", REG_FORMAT_UINT32);
pointMap->add_register("FPGA_xst_subband_select_RW", "fpga/xst_subband_select", nodes.size(), 1+C_N_crosslets_max, "RW", REG_FORMAT_UINT32);
......@@ -141,8 +139,8 @@ Fpga::Fpga(list<class Node*>& nodelist, const int32_t n_beam_sets):
pointMap->add_register("FPGA_scrap_R", "fpga/scrap", nodes.size(), C_N_scrap, "RO", REG_FORMAT_UINT32);
pointMap->add_register("FPGA_scrap_RW", "fpga/scrap", nodes.size(), C_N_scrap, "RW", REG_FORMAT_UINT32);
pointMap->add_register("FPGA_weights_R", "fpga/weights", nodes.size(), C_S_pn*n_beamsets, "RO", REG_FORMAT_INT16);
pointMap->add_register("FPGA_weights_RW", "fpga/weights", nodes.size(), C_S_pn*n_beamsets, "RW", REG_FORMAT_INT16);
pointMap->add_register("FPGA_weights_R", "fpga/weights", nodes.size(), C_S_pn*nBeamsets, "RO", REG_FORMAT_INT16);
pointMap->add_register("FPGA_weights_RW", "fpga/weights", nodes.size(), C_S_pn*nBeamsets, "RW", REG_FORMAT_INT16);
}
Fpga::~Fpga()
......
......@@ -41,12 +41,12 @@
class Fpga
{
private:
int32_t n_beamsets;
int32_t nBeamsets;
std::list<class Node*> FPGA;
CPointMap *pointMap;
public:
Fpga(std::list<class Node*>& nodelist, const int32_t n_beam_sets);
Fpga(std::list<class Node*>& nodelist, const int32_t n_beamsets);
~Fpga();
bool point(TermOutput& termout, const char cmd, const std::string addr,
......
......@@ -150,12 +150,12 @@ void Node::worker()
// << " leaving!!" << endl;
}
Node::Node(const string ipaddr, const uint unb, const uint localnr, const string type, const uint n_beamsets):
Node::Node(const string ipaddr, const uint unb, const uint localnr, const string type, const uint nof_beamsets):
myIPaddr(ipaddr),
UniboardNr(unb),
LocalNr(localnr),
GlobalNr(localnr + 4 * unb),
nBeamsets(n_beamsets)
GlobalNr(localnr + FPGAS_PER_BOARD * unb),
n_beamsets(nof_beamsets)
{
periph_fpga = new Periph_fpga(GlobalNr, ipaddr, n_beamsets);
......
......@@ -101,7 +101,7 @@ class Node {
uint UniboardNr;
uint LocalNr;
uint GlobalNr;
uint nBeamsets;
uint n_beamsets;
std::string Type;
std::thread *worker_thread;
......@@ -116,7 +116,7 @@ class Node {
}
public:
Node(const std::string ipaddr, const uint unb, const uint localnr, const std::string type, const uint n_beamsets);
Node(const std::string ipaddr, const uint unb, const uint localnr, const std::string type, const uint nof_beamsets);
~Node();
uint ipaddr_to_id(const std::string ipaddr);
......
......@@ -207,9 +207,6 @@ bool Periph_fpga::read(TermOutput& termout, const string addr,
else if (addr == "fpga/bst_offload_hdr_udp_destination_port") {
retval = read_bst_offload_hdr_udp_destination_port(termout, format);
}
else if (addr == "fpga/bst_offload_nof_beamlets_per_packet") {
retval = read_bst_offload_nof_beamlets_per_packet(termout, format);
}
else if (addr == "fpga/xst_offload_enable") {
retval = read_xst_offload_enable(termout, format);
}
......@@ -408,9 +405,6 @@ bool Periph_fpga::write(TermOutput& termout, const string addr, const string typ
else if (addr == "fpga/bst_offload_hdr_udp_destination_port") {
retval = write_bst_offload_hdr_udp_destination_port(data);
}
else if (addr == "fpga/bst_offload_nof_beamlets_per_packet") {
retval = write_bst_offload_nof_beamlets_per_packet(data);
}
else if (addr == "fpga/xst_offload_enable") {
retval = write_xst_offload_enable(data);
}
......@@ -1379,40 +1373,6 @@ bool Periph_fpga::write_bst_offload_hdr_udp_destination_port(const char *data)
return retval;
}
bool Periph_fpga::read_bst_offload_nof_beamlets_per_packet(TermOutput& termout, int format)
{
bool retval = true;
string regname;
uint32_t data[20];
int *_ptr = (int *)termout.val;
for (uint32_t i=0; i<nBeamsets; i++) {
memset((void *)data, 0, sizeof(data));
regname = "mm/" + to_string(i) + "/REG_STAT_HDR_DAT_BST/0/TODO";
retval &= Read(regname, data);
int packets = (int)data[i];
*_ptr = packets;
_ptr++;
}
termout.nof_vals = nBeamsets;
termout.datatype = format;
return retval;
}
bool Periph_fpga::write_bst_offload_nof_beamlets_per_packet(const char *data)
{
uint32_t *_ptr = (uint32_t *)data;
bool retval = true;
string regname;
for (uint32_t i=0; i<nBeamsets; i++) {
regname = "mm/" + to_string(i) + "/REG_STAT_HDR_DAT_BST/0/TODO";
if (Write(regname, &_ptr[i]) == false) {
retval = false;
}
}
return retval;
}
bool Periph_fpga::read_xst_offload_enable(TermOutput& termout, int format)
{
bool retval = true;
......
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