Skip to content
Snippets Groups Projects
Commit c0aa39e1 authored by Jan David Mol's avatar Jan David Mol
Browse files

L2SS-358: Added APSCT and APSPU devices, their simulators. Added a common base... 

L2SS-358: Added APSCT and APSPU devices, their simulators. Added a common base image for the pypcc2 simulators. Separated station-dependend configs into separate CDB files. Added OPC-UA node path prefix to support instances with different paths to their nodes.
parent 75ffb1c2
No related branches found
No related tags found
1 merge request!157L2SS-358: Get ready for Darkrai
Hide whitespace changes
Inline Side-by-side
Showing
with 1017 additions and 242 deletions
CDB/Darkrai_ConfigDb.json 0 → 100644
+ 227
− 0
View file @ c0aa39e1
{
"servers": {
"APSCT": {
"LTS": {
"APSCT": {
"LTS/APSCT/1": {
"properties": {
"OPC_Server_Name": [
"despi.astron.nl"
],
"OPC_Server_Port": [
"4843"
],
"OPC_Time_Out": [
"5.0"
]
}
}
}
}
},
"APSPU": {
"LTS": {
"APSPU": {
"LTS/APSPU/1": {
"properties": {
"OPC_Server_Name": [
"despi.astron.nl"
],
"OPC_Server_Port": [
"4842"
],
"OPC_Time_Out": [
"5.0"
]
}
}
}
}
},
"RECV": {
"LTS": {
"RECV": {
"LTS/RECV/1": {
"properties": {
"OPC_Server_Name": [
"ltspi.astron.nl"
],
"OPC_Server_Port": [
"4840"
],
"OPC_Time_Out": [
"5.0"
]
}
}
}
}
},
"SDP": {
"LTS": {
"SDP": {
"LTS/SDP/1": {
"properties": {
"OPC_Server_Name": [
"dop36.astron.nl"
],
"OPC_Server_Port": [
"4840"
],
"OPC_Time_Out": [
"5.0"
],
"FPGA_sdp_info_station_id_RW_default": [
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901"
]
}
}
}
}
},
"SST": {
"LTS": {
"SST": {
"LTS/SST/1": {
"properties": {
"OPC_Server_Name": [
"dop36.astron.nl"
],
"OPC_Server_Port": [
"4840"
],
"OPC_Time_Out": [
"5.0"
],
"FPGA_sst_offload_hdr_eth_destination_mac_RW_default": [
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd"
],
"FPGA_sst_offload_hdr_ip_destination_address_RW_default": [
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250"
]
}
}
}
}
},
"XST": {
"LTS": {
"XST": {
"LTS/XST/1": {
"properties": {
"OPC_Server_Name": [
"dop36.astron.nl"
],
"OPC_Server_Port": [
"4840"
],
"OPC_Time_Out": [
"5.0"
],
"FPGA_xst_offload_hdr_eth_destination_mac_RW_default": [
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd"
],
"FPGA_xst_offload_hdr_ip_destination_address_RW_default": [
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250"
]
}
}
}
}
},
"UNB2": {
"LTS": {
"UNB2": {
"LTS/UNB2/1": {
"properties": {
"OPC_Server_Name": [
"despi.astron.nl"
],
"OPC_Server_Port": [
"4841"
],
"OPC_Time_Out": [
"5.0"
]
}
}
}
}
}
}
}
CDB/LOFAR_ConfigDb.json
+ 21
− 136
View file @ c0aa39e1
......@@ -28,6 +28,26 @@
}
}
},
"APSCT": {
"LTS": {
"APSCT": {
"LTS/APSCT/1": {
"properties": {
}
}
}
}
},
"APSPU": {
"LTS": {
"APSPU": {
"LTS/APSPU/1": {
"properties": {
}
}
}
}
},
"RECV": {
"LTS": {
"RECV": {
......@@ -363,15 +383,6 @@
}
},
"properties": {
"OPC_Server_Name": [
"ltspi.astron.nl"
],
"OPC_Server_Port": [
"4842"
],
"OPC_Time_Out": [
"5.0"
],
"polled_attr": [
"state",
"1000",
......@@ -689,33 +700,6 @@
}
},
"properties": {
"OPC_Server_Name": [
"dop36.astron.nl"
],
"OPC_Server_Port": [
"4840"
],
"OPC_Time_Out": [
"5.0"
],
"FPGA_sdp_info_station_id_RW_default": [
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901"
],
"polled_attr": [
"fpga_temp_r",
"1000",
......@@ -762,51 +746,6 @@
"Statistics_Client_TCP_Port": [
"5101"
],
"OPC_Server_Name": [
"dop36.astron.nl"
],
"OPC_Server_Port": [
"4840"
],
"OPC_Time_Out": [
"5.0"
],
"FPGA_sst_offload_hdr_eth_destination_mac_RW_default": [
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd"
],
"FPGA_sst_offload_hdr_ip_destination_address_RW_default": [
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250"
],
"FPGA_sst_offload_hdr_udp_destination_port_RW_default": [
"5001",
"5001",
......@@ -825,7 +764,7 @@
"5001",
"5001"
]
}
}
}
}
}
......@@ -841,51 +780,6 @@
"Statistics_Client_TCP_Port": [
"5102"
],
"OPC_Server_Name": [
"dop36.astron.nl"
],
"OPC_Server_Port": [
"4840"
],
"OPC_Time_Out": [
"5.0"
],
"FPGA_xst_offload_hdr_eth_destination_mac_RW_default": [
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd"
],
"FPGA_xst_offload_hdr_ip_destination_address_RW_default": [
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250"
],
"FPGA_xst_offload_hdr_udp_destination_port_RW_default": [
"5002",
"5002",
......@@ -914,15 +808,6 @@
"UNB2": {
"LTS/UNB2/1": {
"properties": {
"OPC_Server_Name": [
"despi.astron.nl"
],
"OPC_Server_Port": [
"4842"
],
"OPC_Time_Out": [
"5.0"
]
}
}
}
......
CDB/LTS_ConfigDb.json 0 → 100644
+ 287
− 0
View file @ c0aa39e1
{
"servers": {
"APSCT": {
"LTS": {
"APSCT": {
"LTS/APSCT/1": {
"properties": {
"OPC_Server_Name": [
"ltspi.astron.nl"
],
"OPC_Server_Port": [
"4842"
],
"OPC_Time_Out": [
"5.0"
],
"OPC_Node_Path_prefix": [
"PCC"
]
}
}
}
}
},
"APSPU": {
"LTS": {
"APSPU": {
"LTS/APSPU/1": {
"properties": {
"OPC_Server_Name": [
"ltspi.astron.nl"
],
"OPC_Server_Port": [
"4842"
],
"OPC_Time_Out": [
"5.0"
],
"OPC_Node_Path_prefix": [
"PCC"
]
}
}
}
}
},
"RECV": {
"LTS": {
"RECV": {
"LTS/RECV/1": {
"properties": {
"OPC_Server_Name": [
"ltspi.astron.nl"
],
"OPC_Server_Port": [
"4842"
],
"OPC_Node_Path_prefix": [
"PCC"
],
"OPC_Time_Out": [
"5.0"
]
}
}
}
}
},
"SDP": {
"LTS": {
"SDP": {
"LTS/SDP/1": {
"properties": {
"OPC_Server_Name": [
"dop36.astron.nl"
],
"OPC_Server_Port": [
"4840"
],
"OPC_Time_Out": [
"5.0"
],
"FPGA_sdp_info_station_id_RW_default": [
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901",
"901"
]
}
}
}
}
},
"SST": {
"LTS": {
"SST": {
"LTS/SST/1": {
"properties": {
"Statistics_Client_UDP_Port": [
"5001"
],
"Statistics_Client_TCP_Port": [
"5101"
],
"OPC_Server_Name": [
"dop36.astron.nl"
],
"OPC_Server_Port": [
"4840"
],
"OPC_Time_Out": [
"5.0"
],
"FPGA_sst_offload_hdr_eth_destination_mac_RW_default": [
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd"
],
"FPGA_sst_offload_hdr_ip_destination_address_RW_default": [
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250"
],
"FPGA_sst_offload_hdr_udp_destination_port_RW_default": [
"5001",
"5001",
"5001",
"5001",
"5001",
"5001",
"5001",
"5001",
"5001",
"5001",
"5001",
"5001",
"5001",
"5001",
"5001",
"5001"
]
}
}
}
}
},
"XST": {
"LTS": {
"XST": {
"LTS/XST/1": {
"properties": {
"Statistics_Client_UDP_Port": [
"5002"
],
"Statistics_Client_TCP_Port": [
"5102"
],
"OPC_Server_Name": [
"dop36.astron.nl"
],
"OPC_Server_Port": [
"4840"
],
"OPC_Time_Out": [
"5.0"
],
"FPGA_xst_offload_hdr_eth_destination_mac_RW_default": [
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd",
"6c:2b:59:97:be:dd"
],
"FPGA_xst_offload_hdr_ip_destination_address_RW_default": [
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250",
"10.99.250.250"
],
"FPGA_xst_offload_hdr_udp_destination_port_RW_default": [
"5002",
"5002",
"5002",
"5002",
"5002",
"5002",
"5002",
"5002",
"5002",
"5002",
"5002",
"5002",
"5002",
"5002",
"5002",
"5002"
]
}
}
}
}
},
"UNB2": {
"LTS": {
"UNB2": {
"LTS/UNB2/1": {
"properties": {
"OPC_Server_Name": [
"despi.astron.nl"
],
"OPC_Server_Port": [
"4842"
],
"OPC_Node_Path_prefix": [
"PCC"
],
"OPC_Time_Out": [
"5.0"
]
}
}
}
}
}
}
}
CDB/apsct-sim-config.json 0 → 100644
+ 23
− 0
View file @ c0aa39e1
{
"servers": {
"APSCT": {
"LTS": {
"APSCT": {
"LTS/APSCT/1": {
"properties": {
"OPC_Server_Name": [
"apsct-sim"
],
"OPC_Server_Port": [
"4843"
],
"OPC_Time_Out": [
"5.0"
]
}
}
}
}
}
}
}
CDB/apspu-sim-config.json 0 → 100644
+ 23
− 0
View file @ c0aa39e1
{
"servers": {
"APSPU": {
"LTS": {
"APSPU": {
"LTS/APSPU/1": {
"properties": {
"OPC_Server_Name": [
"apspu-sim"
],
"OPC_Server_Port": [
"4843"
],
"OPC_Time_Out": [
"5.0"
]
}
}
}
}
}
}
}
CDB/integration_ConfigDb.json
+ 40
− 2
View file @ c0aa39e1
{
"servers": {
"APSCT": {
"LTS": {
"APSCT": {
"LTS/APSCT/1": {
"properties": {
"OPC_Server_Name": [
"apsct-sim"
],
"OPC_Server_Port": [
"4843"
],
"OPC_Time_Out": [
"5.0"
]
}
}
}
}
},
"APSPU": {
"LTS": {
"APSPU": {
"LTS/APSPU/1": {
"properties": {
"OPC_Server_Name": [
"apspu-sim"
],
"OPC_Server_Port": [
"4843"
],
"OPC_Time_Out": [
"5.0"
]
}
}
}
}
},
"RECV": {
"LTS": {
"RECV": {
......@@ -9,7 +47,7 @@
"recv-sim"
],
"OPC_Server_Port": [
"4843"
"4840"
],
"OPC_Time_Out": [
"5.0"
......@@ -253,7 +291,7 @@
"unb2-sim"
],
"OPC_Server_Port": [
"4844"
"4841"
],
"OPC_Time_Out": [
"5.0"
......
CDB/recv-sim-config.json
+ 1
− 1
View file @ c0aa39e1
......@@ -9,7 +9,7 @@
"recv-sim"
],
"OPC_Server_Port": [
"4843"
"4840"
],
"OPC_Time_Out": [
"5.0"
......
CDB/unb2-sim-config.json
+ 1
− 1
View file @ c0aa39e1
......@@ -9,7 +9,7 @@
"unb2-sim"
],
"OPC_Server_Port": [
"4844"
"4841"
],
"OPC_Time_Out": [
"5.0"
......
devices/clients/opcua_client.py
+ 20
− 1
View file @ c0aa39e1
......@@ -42,6 +42,9 @@ class OPCUAConnection(AsyncCommClient):
self.client = Client(address, int(timeout))
self.namespace = namespace
# prefix path to all nodes with this. this allows the user to switch trees more easily.
self.node_path_prefix = []
super().__init__(fault_func, event_loop)
def _servername(self):
......@@ -88,7 +91,11 @@ class OPCUAConnection(AsyncCommClient):
except Exception as e:
raise IOError("Lost connection to server %s: %s", self._servername(), e)
async def _setup_annotation(self, annotation):
def get_node_path(self, annotation):
"""
Return the path of a node as it will be looked up on the server.
"""
if isinstance(annotation, dict):
# check if required path inarg is present
if annotation.get('path') is None:
......@@ -100,9 +107,21 @@ class OPCUAConnection(AsyncCommClient):
else:
raise Exception("OPC-ua mapping requires either a list of the path or dict with the path. Was given %s type containing: %s", type(annotation), annotation)
# add path prefix
path = self.node_path_prefix + path
# prepend namespace index for each element if none is given
path = [name if ':' in name else f'{self.name_space_index}:{name}' for name in path]
return path
async def _setup_annotation(self, annotation):
"""
This class's Implementation of the get_mapping function. returns the read and write functions
"""
path = self.get_node_path(annotation)
try:
node = await self.obj.get_child(path)
except Exception as e:
......
devices/devices/apsct.py 0 → 100644
+ 70
− 0
View file @ c0aa39e1
# -*- coding: utf-8 -*-
#
# This file is part of the RECV project
#
#
#
# Distributed under the terms of the APACHE license.
# See LICENSE.txt for more info.
""" APSCT Device Server for LOFAR2.0
"""
# TODO(Corne): Remove sys.path.append hack once packaging is in place!
import os, sys
currentdir = os.path.dirname(os.path.realpath(__file__))
parentdir = os.path.dirname(currentdir)
sys.path.append(parentdir)
# PyTango imports
from tango import DebugIt
from tango.server import run, command
from tango.server import device_property, attribute
from tango import AttrWriteType
import numpy
# Additional import
from device_decorators import *
from clients.attribute_wrapper import attribute_wrapper
from devices.opcua_device import opcua_device
from common.lofar_logging import device_logging_to_python, log_exceptions
__all__ = ["APSCT", "main"]
@device_logging_to_python()
class APSCT(opcua_device):
# -----------------
# Device Properties
# -----------------
# ----------
# Attributes
# ----------
# --------
# overloaded functions
# --------
# --------
# Commands
# --------
pass
# ----------
# Run server
# ----------
def main(args=None, **kwargs):
"""Main function of the APSCT module."""
from common.lofar_logging import configure_logger
configure_logger()
return run((APSCT,), args=args, **kwargs)
if __name__ == '__main__':
main()
devices/devices/apspu.py 0 → 100644
+ 70
− 0
View file @ c0aa39e1
# -*- coding: utf-8 -*-
#
# This file is part of the RECV project
#
#
#
# Distributed under the terms of the APACHE license.
# See LICENSE.txt for more info.
""" APSPU Device Server for LOFAR2.0
"""
# TODO(Corne): Remove sys.path.append hack once packaging is in place!
import os, sys
currentdir = os.path.dirname(os.path.realpath(__file__))
parentdir = os.path.dirname(currentdir)
sys.path.append(parentdir)
# PyTango imports
from tango import DebugIt
from tango.server import run, command
from tango.server import device_property, attribute
from tango import AttrWriteType
import numpy
# Additional import
from device_decorators import *
from clients.attribute_wrapper import attribute_wrapper
from devices.opcua_device import opcua_device
from common.lofar_logging import device_logging_to_python, log_exceptions
__all__ = ["APSPU", "main"]
@device_logging_to_python()
class APSPU(opcua_device):
# -----------------
# Device Properties
# -----------------
# ----------
# Attributes
# ----------
# --------
# overloaded functions
# --------
# --------
# Commands
# --------
pass
# ----------
# Run server
# ----------
def main(args=None, **kwargs):
"""Main function of the APSPU module."""
from common.lofar_logging import configure_logger
configure_logger()
return run((APSPU,), args=args, **kwargs)
if __name__ == '__main__':
main()
devices/devices/boot.py
+ 2
− 0
View file @ c0aa39e1
......@@ -199,6 +199,8 @@ class Boot(hardware_device):
dtype='DevVarStringArray',
mandatory=False,
default_value=["LTS/Docker/1", # Docker controls the device containers, so it goes before anything else
"LTS/APSPU/1", # APS Power Units control other hardware we want to initialise
"LTS/APSCT/1",
"LTS/RECV/1", # RCUs are input for SDP, so initialise them first
"LTS/UNB2/1", # Uniboards host SDP, so initialise them first
"LTS/SDP/1", # SDP controls the mask for SST/XST/BST, so initialise it first
......
devices/devices/docker_device.py
+ 4
− 0
View file @ c0aa39e1
......@@ -54,6 +54,10 @@ class Docker(hardware_device):
archiver_maria_db_RW = attribute_wrapper(comms_annotation={"container": "archiver-maria-db"}, datatype=numpy.bool_, access=AttrWriteType.READ_WRITE)
databaseds_R = attribute_wrapper(comms_annotation={"container": "databaseds"}, datatype=numpy.bool_)
databaseds_RW = attribute_wrapper(comms_annotation={"container": "databaseds"}, datatype=numpy.bool_, access=AttrWriteType.READ_WRITE)
device_apsct_R = attribute_wrapper(comms_annotation={"container": "device-apsct"}, datatype=numpy.bool_)
device_apsct_RW = attribute_wrapper(comms_annotation={"container": "device-apsct"}, datatype=numpy.bool_, access=AttrWriteType.READ_WRITE)
device_apspu_R = attribute_wrapper(comms_annotation={"container": "device-apspu"}, datatype=numpy.bool_)
device_apspu_RW = attribute_wrapper(comms_annotation={"container": "device-apspu"}, datatype=numpy.bool_, access=AttrWriteType.READ_WRITE)
device_recv_R = attribute_wrapper(comms_annotation={"container": "device-recv"}, datatype=numpy.bool_)
device_recv_RW = attribute_wrapper(comms_annotation={"container": "device-recv"}, datatype=numpy.bool_, access=AttrWriteType.READ_WRITE)
device_sdp_R = attribute_wrapper(comms_annotation={"container": "device-sdp"}, datatype=numpy.bool_)
......
devices/devices/opcua_device.py
+ 10
− 1
View file @ c0aa39e1
......@@ -72,6 +72,13 @@ class opcua_device(hardware_device):
default_value="http://lofar.eu"
)
# Add these elements to the OPC-UA node path.
OPC_Node_Path_Prefix = device_property(
dtype='DevVarStringArray',
mandatory=False,
default_value=[]
)
# ----------
# Attributes
# ----------
......@@ -88,6 +95,8 @@ class opcua_device(hardware_device):
# set up the OPC ua client
self.opcua_connection = OPCUAConnection("opc.tcp://{}:{}/".format(self.OPC_Server_Name, self.OPC_Server_Port), self.OPC_namespace, self.OPC_Time_Out, self.Fault)
self.opcua_connection.node_path_prefix = self.OPC_Node_Path_Prefix
self.opcua_missing_attributes = []
# schedule the opc-ua initialisation, and wait for it to finish
......@@ -106,7 +115,7 @@ class opcua_device(hardware_device):
except Exception as e:
# use the pass function instead of setting read/write fails
i.set_pass_func()
self.opcua_missing_attributes.append(",".join(i.comms_annotation))
self.opcua_missing_attributes.append(",".join(self.opcua_connection.get_node_path(i.comms_annotation)))
self.warn_stream("error while setting the attribute {} read/write function. {}".format(i, e))
......
devices/devices/recv.py
+ 32
− 32
View file @ c0aa39e1
......@@ -60,40 +60,40 @@ class RECV(opcua_device):
# ----------
# Attributes
# ----------
Ant_mask_RW = attribute_wrapper(comms_annotation=["2:PCC", "2:Ant_mask_RW"], datatype=numpy.bool_, dims=(3, 32), access=AttrWriteType.READ_WRITE)
Ant_mask_RW = attribute_wrapper(comms_annotation=["2:Ant_mask_RW"], datatype=numpy.bool_, dims=(3, 32), access=AttrWriteType.READ_WRITE)
Ant_status_R = attribute(dtype=str, max_dim_x=3, max_dim_y=32)
CLK_Enable_PWR_R = attribute_wrapper(comms_annotation=["2:PCC", "2:CLK_Enable_PWR_R"], datatype=numpy.bool_)
CLK_I2C_STATUS_R = attribute_wrapper(comms_annotation=["2:PCC", "2:CLK_I2C_STATUS_R"], datatype=numpy.int64)
CLK_PLL_error_R = attribute_wrapper(comms_annotation=["2:PCC", "2:CLK_PLL_error_R"], datatype=numpy.bool_)
CLK_PLL_locked_R = attribute_wrapper(comms_annotation=["2:PCC", "2:CLK_PLL_locked_R"], datatype=numpy.bool_)
CLK_monitor_rate_RW = attribute_wrapper(comms_annotation=["2:PCC", "2:CLK_monitor_rate_RW"], datatype=numpy.int64, access=AttrWriteType.READ_WRITE)
CLK_translator_busy_R = attribute_wrapper(comms_annotation=["2:PCC", "2:CLK_translator_busy_R"], datatype=numpy.bool_)
HBA_element_beamformer_delays_R = attribute_wrapper(comms_annotation=["2:PCC", "2:HBA_element_beamformer_delays_R"], datatype=numpy.int64, dims=(32, 96))
HBA_element_beamformer_delays_RW = attribute_wrapper(comms_annotation=["2:PCC", "2:HBA_element_beamformer_delays_RW"], datatype=numpy.int64, dims=(32, 96), access=AttrWriteType.READ_WRITE)
HBA_element_led_R = attribute_wrapper(comms_annotation=["2:PCC", "2:HBA_element_led_R"], datatype=numpy.int64, dims=(32, 96))
HBA_element_led_RW = attribute_wrapper(comms_annotation=["2:PCC", "2:HBA_element_led_RW"], datatype=numpy.int64, dims=(32, 96), access=AttrWriteType.READ_WRITE)
HBA_element_LNA_pwr_R = attribute_wrapper(comms_annotation=["2:PCC", "2:HBA_element_LNA_pwr_R"], datatype=numpy.int64, dims=(32, 96))
HBA_element_LNA_pwr_RW = attribute_wrapper(comms_annotation=["2:PCC", "2:HBA_element_LNA_pwr_RW"], datatype=numpy.int64, dims=(32, 96), access=AttrWriteType.READ_WRITE)
HBA_element_pwr_R = attribute_wrapper(comms_annotation=["2:PCC", "2:HBA_element_pwr_R"], datatype=numpy.int64, dims=(32, 96))
HBA_element_pwr_RW = attribute_wrapper(comms_annotation=["2:PCC", "2:HBA_element_pwr_RW"], datatype=numpy.int64, dims=(32, 96), access=AttrWriteType.READ_WRITE)
RCU_ADC_lock_R = attribute_wrapper(comms_annotation=["2:PCC", "2:RCU_ADC_lock_R"], datatype=numpy.int64, dims=(3, 32))
RCU_attenuator_R = attribute_wrapper(comms_annotation=["2:PCC", "2:RCU_attenuator_R"], datatype=numpy.int64, dims=(3, 32))
RCU_attenuator_RW = attribute_wrapper(comms_annotation=["2:PCC", "2:RCU_attenuator_RW"], datatype=numpy.int64, dims=(3, 32), access=AttrWriteType.READ_WRITE)
RCU_band_R = attribute_wrapper(comms_annotation=["2:PCC", "2:RCU_band_R"], datatype=numpy.int64, dims=(3, 32))
RCU_band_RW = attribute_wrapper(comms_annotation=["2:PCC", "2:RCU_band_RW"], datatype=numpy.int64, dims=(3, 32), access=AttrWriteType.READ_WRITE)
RCU_I2C_STATUS_R = attribute_wrapper(comms_annotation=["2:PCC", "2:RCU_I2C_STATUS_R"], datatype=numpy.int64, dims=(32,))
RCU_ID_R = attribute_wrapper(comms_annotation=["2:PCC", "2:RCU_ID_R"], datatype=numpy.int64, dims=(32,))
RCU_LED0_R = attribute_wrapper(comms_annotation=["2:PCC", "2:RCU_LED0_R"], datatype=numpy.bool_, dims=(32,))
RCU_LED0_RW = attribute_wrapper(comms_annotation=["2:PCC", "2:RCU_LED0_RW"], datatype=numpy.bool_, dims=(32,), access=AttrWriteType.READ_WRITE)
RCU_LED1_R = attribute_wrapper(comms_annotation=["2:PCC", "2:RCU_LED1_R"], datatype=numpy.bool_, dims=(32,))
RCU_LED1_RW = attribute_wrapper(comms_annotation=["2:PCC", "2:RCU_LED1_RW"], datatype=numpy.bool_, dims=(32,), access=AttrWriteType.READ_WRITE)
RCU_mask_RW = attribute_wrapper(comms_annotation=["2:PCC", "2:RCU_mask_RW"], datatype=numpy.bool_, dims=(32,), access=AttrWriteType.READ_WRITE)
RCU_monitor_rate_RW = attribute_wrapper(comms_annotation=["2:PCC", "2:RCU_monitor_rate_RW"], datatype=numpy.int64, access=AttrWriteType.READ_WRITE)
RCU_Pwr_dig_R = attribute_wrapper(comms_annotation=["2:PCC", "2:RCU_Pwr_dig_R"], datatype=numpy.bool_, dims=(32,))
CLK_Enable_PWR_R = attribute_wrapper(comms_annotation=["2:CLK_Enable_PWR_R"], datatype=numpy.bool_)
CLK_I2C_STATUS_R = attribute_wrapper(comms_annotation=["2:CLK_I2C_STATUS_R"], datatype=numpy.int64)
CLK_PLL_error_R = attribute_wrapper(comms_annotation=["2:CLK_PLL_error_R"], datatype=numpy.bool_)
CLK_PLL_locked_R = attribute_wrapper(comms_annotation=["2:CLK_PLL_locked_R"], datatype=numpy.bool_)
CLK_monitor_rate_RW = attribute_wrapper(comms_annotation=["2:CLK_monitor_rate_RW"], datatype=numpy.int64, access=AttrWriteType.READ_WRITE)
CLK_translator_busy_R = attribute_wrapper(comms_annotation=["2:CLK_translator_busy_R"], datatype=numpy.bool_)
HBA_element_beamformer_delays_R = attribute_wrapper(comms_annotation=["2:HBA_element_beamformer_delays_R"], datatype=numpy.int64, dims=(32, 96))
HBA_element_beamformer_delays_RW = attribute_wrapper(comms_annotation=["2:HBA_element_beamformer_delays_RW"], datatype=numpy.int64, dims=(32, 96), access=AttrWriteType.READ_WRITE)
HBA_element_led_R = attribute_wrapper(comms_annotation=["2:HBA_element_led_R"], datatype=numpy.int64, dims=(32, 96))
HBA_element_led_RW = attribute_wrapper(comms_annotation=["2:HBA_element_led_RW"], datatype=numpy.int64, dims=(32, 96), access=AttrWriteType.READ_WRITE)
HBA_element_LNA_pwr_R = attribute_wrapper(comms_annotation=["2:HBA_element_LNA_pwr_R"], datatype=numpy.int64, dims=(32, 96))
HBA_element_LNA_pwr_RW = attribute_wrapper(comms_annotation=["2:HBA_element_LNA_pwr_RW"], datatype=numpy.int64, dims=(32, 96), access=AttrWriteType.READ_WRITE)
HBA_element_pwr_R = attribute_wrapper(comms_annotation=["2:HBA_element_pwr_R"], datatype=numpy.int64, dims=(32, 96))
HBA_element_pwr_RW = attribute_wrapper(comms_annotation=["2:HBA_element_pwr_RW"], datatype=numpy.int64, dims=(32, 96), access=AttrWriteType.READ_WRITE)
RCU_ADC_lock_R = attribute_wrapper(comms_annotation=["2:RCU_ADC_lock_R"], datatype=numpy.int64, dims=(3, 32))
RCU_attenuator_R = attribute_wrapper(comms_annotation=["2:RCU_attenuator_R"], datatype=numpy.int64, dims=(3, 32))
RCU_attenuator_RW = attribute_wrapper(comms_annotation=["2:RCU_attenuator_RW"], datatype=numpy.int64, dims=(3, 32), access=AttrWriteType.READ_WRITE)
RCU_band_R = attribute_wrapper(comms_annotation=["2:RCU_band_R"], datatype=numpy.int64, dims=(3, 32))
RCU_band_RW = attribute_wrapper(comms_annotation=["2:RCU_band_RW"], datatype=numpy.int64, dims=(3, 32), access=AttrWriteType.READ_WRITE)
RCU_I2C_STATUS_R = attribute_wrapper(comms_annotation=["2:RCU_I2C_STATUS_R"], datatype=numpy.int64, dims=(32,))
RCU_ID_R = attribute_wrapper(comms_annotation=["2:RCU_ID_R"], datatype=numpy.int64, dims=(32,))
RCU_LED0_R = attribute_wrapper(comms_annotation=["2:RCU_LED0_R"], datatype=numpy.bool_, dims=(32,))
RCU_LED0_RW = attribute_wrapper(comms_annotation=["2:RCU_LED0_RW"], datatype=numpy.bool_, dims=(32,), access=AttrWriteType.READ_WRITE)
RCU_LED1_R = attribute_wrapper(comms_annotation=["2:RCU_LED1_R"], datatype=numpy.bool_, dims=(32,))
RCU_LED1_RW = attribute_wrapper(comms_annotation=["2:RCU_LED1_RW"], datatype=numpy.bool_, dims=(32,), access=AttrWriteType.READ_WRITE)
RCU_mask_RW = attribute_wrapper(comms_annotation=["2:RCU_mask_RW"], datatype=numpy.bool_, dims=(32,), access=AttrWriteType.READ_WRITE)
RCU_monitor_rate_RW = attribute_wrapper(comms_annotation=["2:RCU_monitor_rate_RW"], datatype=numpy.int64, access=AttrWriteType.READ_WRITE)
RCU_Pwr_dig_R = attribute_wrapper(comms_annotation=["2:RCU_Pwr_dig_R"], datatype=numpy.bool_, dims=(32,))
Ant_status_R = attribute(dtype=str, max_dim_x=32)
RCU_temperature_R = attribute_wrapper(comms_annotation=["2:PCC", "2:RCU_temperature_R"], datatype=numpy.float64, dims=(32,))
RCU_translator_busy_R = attribute_wrapper(comms_annotation=["2:PCC", "2:RCU_translator_busy_R"], datatype=numpy.bool_)
RCU_version_R = attribute_wrapper(comms_annotation=["2:PCC", "2:RCU_version_R"], datatype=numpy.str, dims=(32,))
RCU_temperature_R = attribute_wrapper(comms_annotation=["2:RCU_temperature_R"], datatype=numpy.float64, dims=(32,))
RCU_translator_busy_R = attribute_wrapper(comms_annotation=["2:RCU_translator_busy_R"], datatype=numpy.bool_)
RCU_version_R = attribute_wrapper(comms_annotation=["2:RCU_version_R"], datatype=numpy.str, dims=(32,))
# --------
# overloaded functions
......
devices/devices/unb2.py
+ 68
− 68
View file @ c0aa39e1
......@@ -61,81 +61,81 @@ class UNB2(opcua_device):
##XXX Means Under discussion
# Special case for the on off switch: instead of UNB2_Power_ON_OFF_R we use UNB2_POL_FPGA_CORE_VOUT_R as the MP
UNB2_Power_ON_OFF_RW = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_Power_ON_OFF_RW"], datatype=numpy.bool_, dims=(N_unb,), access=AttrWriteType.READ_WRITE)
UNB2_Front_Panel_LED_RW = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_Front_Panel_LED_RW"], datatype=numpy.uint8, dims=(N_unb,), access=AttrWriteType.READ_WRITE)
UNB2_Front_Panel_LED_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_Front_Panel_LED_R"], datatype=numpy.uint8, dims=(N_unb,))
UNB2_mask_RW = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_mask_RW"], datatype=numpy.bool_, dims=(N_unb,), access=AttrWriteType.READ_WRITE)
UNB2_Power_ON_OFF_RW = attribute_wrapper(comms_annotation=["2:UNB2_Power_ON_OFF_RW"], datatype=numpy.bool_, dims=(N_unb,), access=AttrWriteType.READ_WRITE)
UNB2_Front_Panel_LED_RW = attribute_wrapper(comms_annotation=["2:UNB2_Front_Panel_LED_RW"], datatype=numpy.uint8, dims=(N_unb,), access=AttrWriteType.READ_WRITE)
UNB2_Front_Panel_LED_R = attribute_wrapper(comms_annotation=["2:UNB2_Front_Panel_LED_R"], datatype=numpy.uint8, dims=(N_unb,))
UNB2_mask_RW = attribute_wrapper(comms_annotation=["2:UNB2_mask_RW"], datatype=numpy.bool_, dims=(N_unb,), access=AttrWriteType.READ_WRITE)
# Not yet deployed
#UNB2_mask_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_mask_R"], datatype=numpy.bool_, dims=(N_unb,))
#UNB2_mask_R = attribute_wrapper(comms_annotation=["2:UNB2_mask_R"], datatype=numpy.bool_, dims=(N_unb,))
### Central MP per Uniboard
# These three are only available in UNB2c
UNB2_I2C_bus_STATUS_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_I2C_bus_STATUS_R"], datatype=numpy.bool_, dims=(N_unb,))
UNB2_I2C_bus_STATUS_R = attribute_wrapper(comms_annotation=["2:UNB2_I2C_bus_STATUS_R"], datatype=numpy.bool_, dims=(N_unb,))
##UNB2_I2C_bus_STATUS_R will probably be renamed to UNB2_I2C_bus_OK_R
##UNB2_I2C_bus_OK_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_I2C_bus_OK_R"], datatype=numpy.bool_, dims=(N_unb,))
#UNB2_EEPROM_Serial_Number_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_EEPROM_Serial_Number_R"], datatype=numpy.str, dims=(N_unb,))
UNB2_EEPROM_Unique_ID_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_EEPROM_Unique_ID_R"], datatype=numpy.uint32, dims=(N_unb,))
UNB2_DC_DC_48V_12V_VIN_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_DC_DC_48V_12V_VIN_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_DC_DC_48V_12V_VOUT_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_DC_DC_48V_12V_VOUT_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_DC_DC_48V_12V_IOUT_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_DC_DC_48V_12V_IOUT_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_DC_DC_48V_12V_TEMP_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_DC_DC_48V_12V_TEMP_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_QSFP_N01_VOUT_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_POL_QSFP_N01_VOUT_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_QSFP_N01_IOUT_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_POL_QSFP_N01_IOUT_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_QSFP_N01_TEMP_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_POL_QSFP_N01_TEMP_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_QSFP_N23_VOUT_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_POL_QSFP_N23_VOUT_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_QSFP_N23_IOUT_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_POL_QSFP_N23_IOUT_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_QSFP_N23_TEMP_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_POL_QSFP_N23_TEMP_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_SWITCH_1V2_VOUT_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_POL_SWITCH_1V2_VOUT_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_SWITCH_1V2_IOUT_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_POL_SWITCH_1V2_IOUT_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_SWITCH_1V2_TEMP_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_POL_SWITCH_1V2_TEMP_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_SWITCH_PHY_VOUT_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_POL_SWITCH_PHY_VOUT_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_SWITCH_PHY_IOUT_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_POL_SWITCH_PHY_IOUT_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_SWITCH_PHY_TEMP_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_POL_SWITCH_PHY_TEMP_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_CLOCK_VOUT_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_POL_CLOCK_VOUT_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_CLOCK_IOUT_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_POL_CLOCK_IOUT_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_CLOCK_TEMP_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_POL_CLOCK_TEMP_R"], datatype=numpy.double, dims=(N_unb,))
##UNB2_I2C_bus_OK_R = attribute_wrapper(comms_annotation=["2:UNB2_I2C_bus_OK_R"], datatype=numpy.bool_, dims=(N_unb,))
#UNB2_EEPROM_Serial_Number_R = attribute_wrapper(comms_annotation=["2:UNB2_EEPROM_Serial_Number_R"], datatype=numpy.str, dims=(N_unb,))
UNB2_EEPROM_Unique_ID_R = attribute_wrapper(comms_annotation=["2:UNB2_EEPROM_Unique_ID_R"], datatype=numpy.uint32, dims=(N_unb,))
UNB2_DC_DC_48V_12V_VIN_R = attribute_wrapper(comms_annotation=["2:UNB2_DC_DC_48V_12V_VIN_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_DC_DC_48V_12V_VOUT_R = attribute_wrapper(comms_annotation=["2:UNB2_DC_DC_48V_12V_VOUT_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_DC_DC_48V_12V_IOUT_R = attribute_wrapper(comms_annotation=["2:UNB2_DC_DC_48V_12V_IOUT_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_DC_DC_48V_12V_TEMP_R = attribute_wrapper(comms_annotation=["2:UNB2_DC_DC_48V_12V_TEMP_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_QSFP_N01_VOUT_R = attribute_wrapper(comms_annotation=["2:UNB2_POL_QSFP_N01_VOUT_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_QSFP_N01_IOUT_R = attribute_wrapper(comms_annotation=["2:UNB2_POL_QSFP_N01_IOUT_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_QSFP_N01_TEMP_R = attribute_wrapper(comms_annotation=["2:UNB2_POL_QSFP_N01_TEMP_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_QSFP_N23_VOUT_R = attribute_wrapper(comms_annotation=["2:UNB2_POL_QSFP_N23_VOUT_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_QSFP_N23_IOUT_R = attribute_wrapper(comms_annotation=["2:UNB2_POL_QSFP_N23_IOUT_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_QSFP_N23_TEMP_R = attribute_wrapper(comms_annotation=["2:UNB2_POL_QSFP_N23_TEMP_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_SWITCH_1V2_VOUT_R = attribute_wrapper(comms_annotation=["2:UNB2_POL_SWITCH_1V2_VOUT_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_SWITCH_1V2_IOUT_R = attribute_wrapper(comms_annotation=["2:UNB2_POL_SWITCH_1V2_IOUT_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_SWITCH_1V2_TEMP_R = attribute_wrapper(comms_annotation=["2:UNB2_POL_SWITCH_1V2_TEMP_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_SWITCH_PHY_VOUT_R = attribute_wrapper(comms_annotation=["2:UNB2_POL_SWITCH_PHY_VOUT_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_SWITCH_PHY_IOUT_R = attribute_wrapper(comms_annotation=["2:UNB2_POL_SWITCH_PHY_IOUT_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_SWITCH_PHY_TEMP_R = attribute_wrapper(comms_annotation=["2:UNB2_POL_SWITCH_PHY_TEMP_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_CLOCK_VOUT_R = attribute_wrapper(comms_annotation=["2:UNB2_POL_CLOCK_VOUT_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_CLOCK_IOUT_R = attribute_wrapper(comms_annotation=["2:UNB2_POL_CLOCK_IOUT_R"], datatype=numpy.double, dims=(N_unb,))
UNB2_POL_CLOCK_TEMP_R = attribute_wrapper(comms_annotation=["2:UNB2_POL_CLOCK_TEMP_R"], datatype=numpy.double, dims=(N_unb,))
### Local MP per FPGA
UNB2_FPGA_DDR4_SLOT_TEMP_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_DDR4_SLOT_TEMP_R"], datatype=numpy.double, dims=((N_fpga * N_ddr), N_unb))
#UNB2_FPGA_DDR4_SLOT_PART_NUMBER_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_DDR4_SLOT_PART_NUMBER_R"], datatype=numpy.str, dims=(N_fpga * N_ddr), N_unb))
#UNB2_FPGA_QSFP_CAGE_TEMP_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_QSFP_CAGE_0_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_1_TEMP_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_QSFP_CAGE_1_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_2_TEMP_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_QSFP_CAGE_2_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_3_TEMP_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_QSFP_CAGE_3_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_4_TEMP_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_QSFP_CAGE_4_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_5_TEMP_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_QSFP_CAGE_5_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_LOS_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_QSFP_CAGE_0_LOS_R"], datatype=numpy.uint8, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_1_LOS_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_QSFP_CAGE_1_LOS_R"], datatype=numpy.uint8, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_2_LOS_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_QSFP_CAGE_2_LOS_R"], datatype=numpy.uint8, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_3_LOS_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_QSFP_CAGE_3_LOS_R"], datatype=numpy.uint8, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_4_LOS_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_QSFP_CAGE_4_LOS_R"], datatype=numpy.uint8, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_5_LOS_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_QSFP_CAGE_5_LOS_R"], datatype=numpy.uint8, dims=(N_fpga, N_unb))
#UNB2_FPGA_POL_CORE_VOUT_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_POL_FPGA_CORE_VOUT_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_CORE_IOUT_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_POL_CORE_IOUT_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_CORE_TEMP_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_POL_CORE_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_ERAM_VOUT_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_POL_ERAM_VOUT_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_ERAM_IOUT_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_POL_ERAM_IOUT_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_ERAM_TEMP_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_POL_ERAM_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_RXGXB_VOUT_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_POL_RXGXB_VOUT_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_RXGXB_IOUT_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_POL_RXGXB_IOUT_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_RXGXB_TEMP_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_POL_RXGXB_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_TXGXB_VOUT_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_POL_TXGXB_VOUT_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_TXGXB_IOUT_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_POL_TXGXB_IOUT_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
#UNB2_FPGA_POL_TXGXB_TEMP_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_POL_FPGA_TXGXB_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_HGXB_VOUT_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_POL_HGXB_VOUT_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_HGXB_IOUT_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_POL_HGXB_IOUT_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_HGXB_TEMP_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_POL_HGXB_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_PGM_VOUT_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_POL_PGM_VOUT_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_PGM_IOUT_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_POL_PGM_IOUT_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_PGM_TEMP_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_FPGA_POL_PGM_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
##UNB2_I2C_bus_QSFP_STATUS_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_I2C_bus_QSFP_STATUS_R"], datatype=numpy.int64, dims=((N_unb * N_fpga), N_qsfp))
##UNB2_I2C_bus_DDR4_STATUS_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_I2C_bus_DDR4_STATUS_R"], datatype=numpy.int64, dims=(N_ddr, N_fpga))
##UNB2_I2C_bus_FPGA_PS_STATUS_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_I2C_bus_FPGA_PS_STATUS_R"], datatype=numpy.int64, dims=(N_unb * N_fpga,))
##UNB2_I2C_bus_PS_STATUS_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_I2C_bus_PS_STATUS_R"], datatype=numpy.double, dims=(N_unb,))
##UNB2_translator_busy_R = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_translator_busy_R"], datatype=numpy.bool_)
##UNB2_monitor_rate_RW = attribute_wrapper(comms_annotation=["2:PCC", "2:UNB2_monitor_rate_RW"], datatype=numpy.double, dims=(N_unb,), access=AttrWriteType.READ_WRITE)
UNB2_FPGA_DDR4_SLOT_TEMP_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_DDR4_SLOT_TEMP_R"], datatype=numpy.double, dims=((N_fpga * N_ddr), N_unb))
#UNB2_FPGA_DDR4_SLOT_PART_NUMBER_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_DDR4_SLOT_PART_NUMBER_R"], datatype=numpy.str, dims=(N_fpga * N_ddr), N_unb))
#UNB2_FPGA_QSFP_CAGE_TEMP_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_QSFP_CAGE_0_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_1_TEMP_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_QSFP_CAGE_1_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_2_TEMP_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_QSFP_CAGE_2_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_3_TEMP_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_QSFP_CAGE_3_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_4_TEMP_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_QSFP_CAGE_4_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_5_TEMP_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_QSFP_CAGE_5_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_LOS_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_QSFP_CAGE_0_LOS_R"], datatype=numpy.uint8, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_1_LOS_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_QSFP_CAGE_1_LOS_R"], datatype=numpy.uint8, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_2_LOS_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_QSFP_CAGE_2_LOS_R"], datatype=numpy.uint8, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_3_LOS_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_QSFP_CAGE_3_LOS_R"], datatype=numpy.uint8, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_4_LOS_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_QSFP_CAGE_4_LOS_R"], datatype=numpy.uint8, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_5_LOS_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_QSFP_CAGE_5_LOS_R"], datatype=numpy.uint8, dims=(N_fpga, N_unb))
#UNB2_FPGA_POL_CORE_VOUT_R = attribute_wrapper(comms_annotation=["2:UNB2_POL_FPGA_CORE_VOUT_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_CORE_IOUT_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_POL_CORE_IOUT_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_CORE_TEMP_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_POL_CORE_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_ERAM_VOUT_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_POL_ERAM_VOUT_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_ERAM_IOUT_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_POL_ERAM_IOUT_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_ERAM_TEMP_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_POL_ERAM_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_RXGXB_VOUT_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_POL_RXGXB_VOUT_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_RXGXB_IOUT_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_POL_RXGXB_IOUT_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_RXGXB_TEMP_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_POL_RXGXB_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_TXGXB_VOUT_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_POL_TXGXB_VOUT_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_TXGXB_IOUT_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_POL_TXGXB_IOUT_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
#UNB2_FPGA_POL_TXGXB_TEMP_R = attribute_wrapper(comms_annotation=["2:UNB2_POL_FPGA_TXGXB_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_HGXB_VOUT_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_POL_HGXB_VOUT_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_HGXB_IOUT_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_POL_HGXB_IOUT_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_HGXB_TEMP_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_POL_HGXB_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_PGM_VOUT_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_POL_PGM_VOUT_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_PGM_IOUT_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_POL_PGM_IOUT_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_PGM_TEMP_R = attribute_wrapper(comms_annotation=["2:UNB2_FPGA_POL_PGM_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
##UNB2_I2C_bus_QSFP_STATUS_R = attribute_wrapper(comms_annotation=["2:UNB2_I2C_bus_QSFP_STATUS_R"], datatype=numpy.int64, dims=((N_unb * N_fpga), N_qsfp))
##UNB2_I2C_bus_DDR4_STATUS_R = attribute_wrapper(comms_annotation=["2:UNB2_I2C_bus_DDR4_STATUS_R"], datatype=numpy.int64, dims=(N_ddr, N_fpga))
##UNB2_I2C_bus_FPGA_PS_STATUS_R = attribute_wrapper(comms_annotation=["2:UNB2_I2C_bus_FPGA_PS_STATUS_R"], datatype=numpy.int64, dims=(N_unb * N_fpga,))
##UNB2_I2C_bus_PS_STATUS_R = attribute_wrapper(comms_annotation=["2:UNB2_I2C_bus_PS_STATUS_R"], datatype=numpy.double, dims=(N_unb,))
##UNB2_translator_busy_R = attribute_wrapper(comms_annotation=["2:UNB2_translator_busy_R"], datatype=numpy.bool_)
##UNB2_monitor_rate_RW = attribute_wrapper(comms_annotation=["2:UNB2_monitor_rate_RW"], datatype=numpy.double, dims=(N_unb,), access=AttrWriteType.READ_WRITE)
# QualifiedName(2: UNB2_on)
# QualifiedName(2: UNB2_off)
......
docker-compose/apsct-sim.yml 0 → 100644
+ 17
− 0
View file @ c0aa39e1
#
# Docker compose file that launches an APSCT simulator
#
# Defines:
# - apsct-sim
#
version: '2'
services:
apsct-sim:
build:
context: pypcc-sim-base
container_name: ${CONTAINER_NAME_PREFIX}apsct-sim
networks:
- control
entrypoint: python3 pypcc2.py --simulator --port 4843 --config APSCTTR
restart: on-failure
docker-compose/apspu-sim.yml 0 → 100644
+ 17
− 0
View file @ c0aa39e1
#
# Docker compose file that launches an APSPU simulator
#
# Defines:
# - apspu-sim
#
version: '2'
services:
apspu-sim:
build:
context: pypcc-sim-base
container_name: ${CONTAINER_NAME_PREFIX}apspu-sim
networks:
- control
entrypoint: python3 pypcc2.py --simulator --port 4842 --config APSPUTR
restart: on-failure
docker-compose/device-apsct.yml 0 → 100644
+ 42
− 0
View file @ c0aa39e1
#
# Docker compose file that launches an interactive iTango session.
#
# Connect to the interactive session with 'docker attach itango'.
# Disconnect with the Docker deattach sequence: <CTRL>+<P> <CTRL>+<Q>
#
# Defines:
# - itango: iTango interactive session
#
# Requires:
# - lofar-device-base.yml
#
version: '2'
services:
device-apsct:
image: device-apsct
# build explicitly, as docker-compose does not understand a local image
# being shared among services.
build:
context: lofar-device-base
args:
SOURCE_IMAGE: ${DOCKER_REGISTRY_HOST}/${DOCKER_REGISTRY_USER}-tango-itango:${TANGO_ITANGO_VERSION}
container_name: ${CONTAINER_NAME_PREFIX}device-apsct
networks:
- control
ports:
- "5709:5709" # unique port for this DS
volumes:
- ..:/opt/lofar/tango:rw
environment:
- TANGO_HOST=${TANGO_HOST}
entrypoint:
- /usr/local/bin/wait-for-it.sh
- ${TANGO_HOST}
- --timeout=30
- --strict
- --
# configure CORBA to _listen_ on 0:port, but tell others we're _reachable_ through ${HOSTNAME}:port, since CORBA
# can't know about our Docker port forwarding
- python3 -u /opt/lofar/tango/devices/devices/apsct.py LTS -v -ORBendPoint giop:tcp:0:5709 -ORBendPointPublish giop:tcp:${HOSTNAME}:5709
restart: on-failure
docker-compose/device-apspu.yml 0 → 100644
+ 42
− 0
View file @ c0aa39e1
#
# Docker compose file that launches an interactive iTango session.
#
# Connect to the interactive session with 'docker attach itango'.
# Disconnect with the Docker deattach sequence: <CTRL>+<P> <CTRL>+<Q>
#
# Defines:
# - itango: iTango interactive session
#
# Requires:
# - lofar-device-base.yml
#
version: '2'
services:
device-apspu:
image: device-apspu
# build explicitly, as docker-compose does not understand a local image
# being shared among services.
build:
context: lofar-device-base
args:
SOURCE_IMAGE: ${DOCKER_REGISTRY_HOST}/${DOCKER_REGISTRY_USER}-tango-itango:${TANGO_ITANGO_VERSION}
container_name: ${CONTAINER_NAME_PREFIX}device-apspu
networks:
- control
ports:
- "5710:5710" # unique port for this DS
volumes:
- ..:/opt/lofar/tango:rw
environment:
- TANGO_HOST=${TANGO_HOST}
entrypoint:
- /usr/local/bin/wait-for-it.sh
- ${TANGO_HOST}
- --timeout=30
- --strict
- --
# configure CORBA to _listen_ on 0:port, but tell others we're _reachable_ through ${HOSTNAME}:port, since CORBA
# can't know about our Docker port forwarding
- python3 -u /opt/lofar/tango/devices/devices/apspu.py LTS -v -ORBendPoint giop:tcp:0:5710 -ORBendPointPublish giop:tcp:${HOSTNAME}:5710
restart: on-failure
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment