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Commit 8846c3d0 authored by Taya Snijder's avatar Taya Snijder
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removed jupyter notebook

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1 merge request!188Resolve L2SS-461 "Replace percentage s with f in logging"
%% Cell type:markdown id:6bdc7054 tags:
# Test LRx.y: Test Name
This notebook documents test output.
Instructions:
1. *PRESS File -> Make a Copy*,
1. Rename the notebook to the name of the test,
1. Update the title at the top of this section,
1. Fill in the sections with empty blocks with code and text,
1. Execute the provided initialisation code,
1. Run the tests,
1. *Rerun everything top to bottom to make sure the notebook is correct*,
1. Fill in the results & verdict.
1. ...and you're done!
%% Cell type:markdown id:0b4a59a5 tags:
## Purpose
(Describe the purpose and context of this notebook, possibly including any links to external references)
%% Cell type:markdown id:09d4d0a1 tags:
cfdsadasd asdasd asd
%% Cell type:markdown id:4c6489f3 tags:
## Methodology
Summary of how we are going to prove compliance.
%% Cell type:code id:8f47dc0a tags:
``` python
# A number of status monitor points were added to the tango device.
# These points should be relatively simple read only points.
# Simply successfully reading them should demonstrate thatour device is working correctly
```
%% Output
File "/tmp/ipykernel_453/2085207180.py", line 1
sdfsd sdfs dfsd sdf
^
SyntaxError: invalid syntax
%% Cell type:markdown id:9033f262 tags:
## Initialisation
The following sections contain boilerplate code to get the station to a well-defined state, and to get core configuration information in the report.
%% Cell type:markdown id:ff837bcb tags:
### Who and when
This test was executed by xxxxxxx
%% Cell type:code id:00418ee4 tags:
``` python
import datetime
print(f"Test was executed at {datetime.datetime.isoformat(datetime.datetime.now(), ' ')}")
```
%% Output
Test was executed at 2021-11-15 14:23:18.156584
%% Cell type:markdown id:7532d05e tags:
### Hot reboot
Makes sure the software and hardware are all in a known state.
%% Cell type:code id:c7a3effa tags:
``` python
# Restart boot device
boot.off()
boot.initialise()
boot.on()
```
%% Output
---------------------------------------------------------------------------
NameError Traceback (most recent call last)
/tmp/ipykernel_32/4020222899.py in <module>
1 # Restart boot device
----> 2 boot.off()
3 boot.initialise()
4 boot.on()
NameError: name 'boot' is not defined
%% Cell type:code id:b4dd21b1 tags:
``` python
# Reboot the station
boot.initialise_station()
```
%% Cell type:code id:78a4db84 tags:
``` python
# Wait for reboot to complete
import time
while boot.initialising_station_R:
time.sleep(2)
print(f"Initialisation at {boot.initialisation_progress_R}%: {boot.initialisation_status_R}")
assert boot.initialisation_progress_R == 100, "Failed to fully initialise station."
```
%% Output
Initialisation at 100%: Initialisation completed
%% Cell type:markdown id:9bc072af tags:
### Active versions
List the versions currently running on the station.
%% Cell type:code id:35b815d4 tags:
``` python
def summarise(l: list) -> list:
return [f"{idx}: {version}" for idx,version in enumerate(l) if version] or ["no versions reported"]
versions = {
"SC": {dev.name():dev.version_R for dev in devices},
"SDP": {
"FPGA firmware": summarise(sdp.FPGA_firmware_version_R),
"FPGA hardware": summarise(sdp.FPGA_hardware_version_R),
"SDPTR": sdp.TR_software_version_R,
},
"""
NOTE: These were not functional and are simply commented out due to not being relevant to the test.
"""
# "RECV": {
# "PCB": summarise(recv.RCU_PCB_version_R),
# },
# "APSCT": {
# "PCB": apsct.APSCT_PCB_version_R,
# },
# "APSPU": {
# "PCB": apspu.APSPU_PCB_version_R,
# },
# "UNB2": {
# "PCB": summarise(unb2.UNB2_PCB_version_R),
# }
}
from pprint import pprint
pprint(versions, width=120)
```
%% Output
{'SC': {'LTS/Boot/1': '*master [2480b2f87d203d39ae5c774c33b985e56a55ba0a]',
'LTS/Docker/1': '*master [2480b2f87d203d39ae5c774c33b985e56a55ba0a]',
'LTS/RECV/1': '*master [d13e50de3efee0aee9aa110d054981980fbebf3f]',
'LTS/SDP/1': '*master [2480b2f87d203d39ae5c774c33b985e56a55ba0a]',
'LTS/SST/1': '*master [2480b2f87d203d39ae5c774c33b985e56a55ba0a]',
'LTS/UNB2/1': '*master [2480b2f87d203d39ae5c774c33b985e56a55ba0a]',
'LTS/XST/1': '*master [2480b2f87d203d39ae5c774c33b985e56a55ba0a]'},
'SDP': {'FPGA firmware': ['8: 2021-10-21T15.10.06_878797106_lofar2_unb2b_sdp_station_full',
'9: 2021-10-02T11.38.05_828519012_lofar2_unb2b_sdp_station_full',
'10: 2021-10-06T15.45.41_808990001_lofar2_unb2b_sdp_station_full',
'11: 2021-10-06T15.45.41_808990001_lofar2_unb2b_sdp_station_full'],
'FPGA hardware': ['8: UniBoard2b', '9: UniBoard2b', '10: UniBoard2b', '11: UniBoard2b'],
'SDPTR': 'git'}}
%% Cell type:markdown id:e51a06b7 tags:
## Test setup
Setup the hardware for the test, with comments about what's happening.
%% Cell type:code id:e72dc2df tags:
``` python
import time
import numpy
sdp=DeviceProxy("STAT/SDP/1")
state = str(sdp.state())
if state == "OFF":
sdp.initialise()
time.sleep(1)
state = str(sdp.state())
if state == "STANDBY":
sdp.on()
state = str(sdp.state())
print(f"{sdp.name} now in {sdp.state()} state")
```
%% Output
<bound method name of SDP(stat/sdp/1)> now in ON state
%% Cell type:markdown id:772dff7c tags:
## Run test
Run the actual test. It is acceptable if the line between setup and test is a bit blurry.
%% Cell type:code id:9f117b2a tags:
``` python
a = []
```
%% Cell type:code id:26570aea tags:
``` python
a.append(f"FPGA_signal_input_mean_R: {sdp.FPGA_signal_input_mean_R} ")
```
%% Cell type:code id:e79b83a0 tags:
``` python
a.append(f"FPGA_signal_input_rms_R: {sdp.FPGA_signal_input_rms_R} ")
```
%% Cell type:code id:ec062564 tags:
``` python
a.append(f"FPGA_jesd204b_csr_rbd_count_R: {sdp.FPGA_jesd204b_csr_rbd_count_R} ")
```
%% Cell type:code id:860c75ba tags:
``` python
a.append(f"FPGA_jesd204b_csr_dev_syncn_R: {sdp.FPGA_jesd204b_csr_dev_syncn_R} ")
```
%% Cell type:code id:47be40db tags:
``` python
a.append(f"FPGA_jesd204b_rx_err0_R: {sdp.FPGA_jesd204b_rx_err0_R} ")
```
%% Cell type:code id:796025cc tags:
``` python
a.append(f"FPGA_jesd204b_rx_err1_R: {sdp.FPGA_jesd204b_rx_err1_R} ")
```
%% Cell type:code id:c9aa54ba tags:
``` python
a.append(f"FPGA_bsn_monitor_input_bsn_R: {sdp.FPGA_bsn_monitor_input_bsn_R} ")
```
%% Cell type:code id:29ff56ef tags:
``` python
a.append(f"FPGA_bsn_monitor_input_nof_packets_R: {sdp.FPGA_bsn_monitor_input_nof_packets_R} ")
```
%% Cell type:code id:82d56a27 tags:
``` python
a.append(f"FPGA_bsn_monitor_input_nof_valid_R: {sdp.FPGA_bsn_monitor_input_nof_valid_R} ")
```
%% Cell type:code id:71c82fd3 tags:
``` python
a.append(f"FPGA_bsn_monitor_input_nof_err_R: {sdp.FPGA_bsn_monitor_input_nof_err_R} ")
```
%% Cell type:markdown id:6c604116 tags:
## Test results
Print the results of the test.
%% Cell type:code id:d290d8dd tags:
``` python
for i in a:
print(i)
```
%% Output
FPGA_signal_input_mean_R: [[ 0. 0. 0. 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 0. 0. 0. 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 0. 0. 0. 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 0. 0. 0. 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 0. 0. 0. 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 0. 0. 0. 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 0. 0. 0. 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 0. 0. 0. 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 4.05462319 -17.41039919 -10.71404389 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 0. 0. 0. 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 9.65630385 21.5598806 12.9992259 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 11.11017832 15.05460048 1.26581269 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 0. 0. 0. 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 0. 0. 0. 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 0. 0. 0. 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 0. 0. 0. 0. 0.
0. 0. 0. 0. 0.
0. 0. ]]
FPGA_signal_input_rms_R: [[ 0. 0. 0. 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 0. 0. 0. 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 0. 0. 0. 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 0. 0. 0. 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 0. 0. 0. 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 0. 0. 0. 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 0. 0. 0. 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 0. 0. 0. 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 4.4754077 17.38906716 10.77156682 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 0. 0. 0. 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[830.79833776 683.13870406 824.89582177 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 11.29810053 15.09288031 2.28362144 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 0. 0. 0. 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 0. 0. 0. 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 0. 0. 0. 0. 0.
0. 0. 0. 0. 0.
0. 0. ]
[ 0. 0. 0. 0. 0.
0. 0. 0. 0. 0.
0. 0. ]]
FPGA_jesd204b_csr_rbd_count_R: [[0 0 0 0 0 0 0 0 0 0 0 0]
[0 0 0 0 0 0 0 0 0 0 0 0]
[0 0 0 0 0 0 0 0 0 0 0 0]
[0 0 0 0 0 0 0 0 0 0 0 0]
[0 0 0 0 0 0 0 0 0 0 0 0]
[0 0 0 0 0 0 0 0 0 0 0 0]
[0 0 0 0 0 0 0 0 0 0 0 0]
[0 0 0 0 0 0 0 0 0 0 0 0]
[2 2 2 0 0 0 0 0 0 0 0 0]
[0 0 0 0 0 0 0 0 0 0 0 0]
[3 2 2 0 0 0 0 0 0 0 0 0]
[2 2 2 0 0 0 0 0 0 0 0 0]
[0 0 0 0 0 0 0 0 0 0 0 0]
[0 0 0 0 0 0 0 0 0 0 0 0]
[0 0 0 0 0 0 0 0 0 0 0 0]
[0 0 0 0 0 0 0 0 0 0 0 0]]
FPGA_jesd204b_csr_dev_syncn_R: [[0 0 0 0 0 0 0 0 0 0 0 0]
[0 0 0 0 0 0 0 0 0 0 0 0]
[0 0 0 0 0 0 0 0 0 0 0 0]
[0 0 0 0 0 0 0 0 0 0 0 0]
[0 0 0 0 0 0 0 0 0 0 0 0]
[0 0 0 0 0 0 0 0 0 0 0 0]
[0 0 0 0 0 0 0 0 0 0 0 0]
[0 0 0 0 0 0 0 0 0 0 0 0]
[1 1 1 0 0 0 0 0 0 0 0 0]
[0 0 0 0 0 0 0 0 0 0 0 0]
[1 1 1 0 0 0 0 0 0 0 0 0]
[1 1 1 0 0 0 0 0 0 0 0 0]
[0 0 0 0 0 0 0 0 0 0 0 0]
[0 0 0 0 0 0 0 0 0 0 0 0]
[0 0 0 0 0 0 0 0 0 0 0 0]
[0 0 0 0 0 0 0 0 0 0 0 0]]
FPGA_jesd204b_rx_err0_R: [[ 0 0 0 0 0 0 0 0 0 0 0 0]
[ 0 0 0 0 0 0 0 0 0 0 0 0]
[ 0 0 0 0 0 0 0 0 0 0 0 0]
[ 0 0 0 0 0 0 0 0 0 0 0 0]
[ 0 0 0 0 0 0 0 0 0 0 0 0]
[ 0 0 0 0 0 0 0 0 0 0 0 0]
[ 0 0 0 0 0 0 0 0 0 0 0 0]
[ 0 0 0 0 0 0 0 0 0 0 0 0]
[ 0 0 0 224 224 224 96 224 224 224 224 224]
[ 0 0 0 0 0 0 0 0 0 0 0 0]
[ 0 0 0 224 160 224 160 224 224 96 160 224]
[ 0 0 0 224 224 224 224 224 160 160 224 224]
[ 0 0 0 0 0 0 0 0 0 0 0 0]
[ 0 0 0 0 0 0 0 0 0 0 0 0]
[ 0 0 0 0 0 0 0 0 0 0 0 0]
[ 0 0 0 0 0 0 0 0 0 0 0 0]]
FPGA_jesd204b_rx_err1_R: [[ 0 0 0 0 0 0 0 0 0 0 0 0]
[ 0 0 0 0 0 0 0 0 0 0 0 0]
[ 0 0 0 0 0 0 0 0 0 0 0 0]
[ 0 0 0 0 0 0 0 0 0 0 0 0]
[ 0 0 0 0 0 0 0 0 0 0 0 0]
[ 0 0 0 0 0 0 0 0 0 0 0 0]
[ 0 0 0 0 0 0 0 0 0 0 0 0]
[ 0 0 0 0 0 0 0 0 0 0 0 0]
[ 0 0 0 49 49 57 0 56 56 56 0 56]
[ 0 0 0 0 0 0 0 0 0 0 0 0]
[ 0 0 0 0 56 56 0 56 0 0 0 56]
[ 0 0 0 0 56 56 56 0 56 0 0 0]
[ 0 0 0 0 0 0 0 0 0 0 0 0]
[ 0 0 0 0 0 0 0 0 0 0 0 0]
[ 0 0 0 0 0 0 0 0 0 0 0 0]
[ 0 0 0 0 0 0 0 0 0 0 0 0]]
FPGA_bsn_monitor_input_bsn_R: [ 0 0 0 0
0 0 0 0
319517661914062 0 319517661914062 319517661914062
0 0 0 0]
FPGA_bsn_monitor_input_nof_packets_R: [ 0 0 0 0 0 0 0 0 195312 0
195312 195312 0 0 0 0]
FPGA_bsn_monitor_input_nof_valid_R: [ 0 0 0 0 0 0 0
0 199999488 0 199999488 199999488 0 0
0 0]
FPGA_bsn_monitor_input_nof_err_R: [0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
%% Cell type:markdown id:d3cdb620 tags:
## Discuss results
How should the results be interpreted? Are there remaining worries and todo's based on this result?
%% Cell type:code id:dbe34d41 tags:
``` python
# Reading was succesful, thats as far as we need to go. The values we're reading out doesn't concern this ticket.
# Additionally the fact that only [8] [10] and [11] show any values shows that we are indeed getting the proper values
# since currently those are the only inputs that are set up and active.
```
%% Cell type:markdown id:a95fbf48 tags:
## Verdict
Did the test pass, and why (not)?
%% Cell type:code id:ccd3c506 tags:
``` python
# The test passed. The goal of this test was to be able to read out all the added monitor points, and this succeeded.
```
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