L2SS-394: Set sane defaults for WG, fix FPGA_xst_integration_level dimensions

devices/devices/sdp/sdp.py

@@ -56,6 +56,27 @@ class SDP(opcua_device):
         mandatory=False,
         default_value=[[False] * 12] * 16
     )
+
+    # If we enable the waveform generator, we want some sane defaults.
+
+    FPGA_wg_amplitude_RW = device_property(
+        dtype='DevVarDoubleArray',
+        mandatory=False,
+        default_value=[[0.1] * 12] * 16
+    )
+
+    FPGA_wg_frequency_RW = device_property(
+        dtype='DevVarDoubleArray',
+        mandatory=False,
+        # Emit a signal on subband 102
+        default_value=[[102 * 200e6/1024] * 12] * 16
+    )
+
+    FPGA_wg_phase_RW = device_property(
+        dtype='DevVarDoubleArray',
+        mandatory=False,
+        default_value=[[0.0] * 12] * 16
+    )
     
     FPGA_sdp_info_station_id_RW_default = device_property(
         dtype='DevVarULongArray',

devices/devices/sdp/xst.py

@@ -75,6 +75,12 @@ class XST(Statistics):
         default_value=[[0,102,0,0,0,0,0,0]] * 16
     )
 
+    FPGA_xst_integration_interval_RW_default = device_property(
+        dtype='DevVarDoubleArray',
+        mandatory=False,
+        default_value=[1.0] * 16
+    )
+
     FPGA_xst_offload_enable_RW_default = device_property(
         dtype='DevVarBooleanArray',
         mandatory=False,
@@ -87,6 +93,7 @@ class XST(Statistics):
         'FPGA_xst_offload_hdr_udp_destination_port_RW',
 
         'FPGA_xst_subband_select_RW',
+        'FPGA_xst_integration_interval_RW',
 
         # enable only after the offloading is configured correctly
         'FPGA_xst_offload_enable_RW'
@@ -97,8 +104,8 @@ class XST(Statistics):
     # ----------
 
     # FPGA control points for XSTs
-    FPGA_xst_integration_interval_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_xst_integration_interval_RW"], datatype=numpy.double, dims=(8,16), access=AttrWriteType.READ_WRITE)
-    FPGA_xst_integration_interval_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_xst_integration_interval_R"], datatype=numpy.double, dims=(8,16))
+    FPGA_xst_integration_interval_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_xst_integration_interval_RW"], datatype=numpy.double, dims=(16,), access=AttrWriteType.READ_WRITE)
+    FPGA_xst_integration_interval_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_xst_integration_interval_R"], datatype=numpy.double, dims=(16,))
     FPGA_xst_offload_enable_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_xst_offload_enable_RW"], datatype=numpy.bool_, dims=(16,), access=AttrWriteType.READ_WRITE)
     FPGA_xst_offload_enable_R = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_xst_offload_enable_R"], datatype=numpy.bool_, dims=(16,))
     FPGA_xst_offload_hdr_eth_destination_mac_RW = attribute_wrapper(comms_id=OPCUAConnection, comms_annotation=["2:FPGA_xst_offload_hdr_eth_destination_mac_RW"], datatype=numpy.str, dims=(16,), access=AttrWriteType.READ_WRITE)