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Commit 5ee4911b authored by Jan David Mol's avatar Jan David Mol
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Updated DTS configuration

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CDB/stations/DTS.json
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...@@ -7,12 +7,13 @@ ...@@ -7,12 +7,13 @@
"properties": { "properties": {
"Power_Children": [ "Power_Children": [
"STAT/EC/1", "STAT/EC/1",
"STAT/Configuration/1",
"STAT/Calibration/1",
"STAT/ObservationControl/1",
"STAT/TemperatureManager/1", "STAT/TemperatureManager/1",
"STAT/AFL/LBA", "STAT/AFL/LBA",
"STAT/AFH/HBA" "STAT/AFH/HBA0",
"STAT/AFH/HBA1",
"STAT/Calibration/1",
"STAT/ObservationControl/1",
"STAT/Configuration/1"
], ],
"Control_Children": [ "Control_Children": [
"STAT/EC/1", "STAT/EC/1",
...@@ -23,11 +24,12 @@ ...@@ -23,11 +24,12 @@
"STAT/Calibration/1", "STAT/Calibration/1",
"STAT/ObservationControl/1", "STAT/ObservationControl/1",
"STAT/TemperatureManager/1", "STAT/TemperatureManager/1",
"STAT/AFL/LBA",
"STAT/AFH/HBA",
"STAT/APS/L0", "STAT/APS/L0",
"STAT/APS/L1", "STAT/APS/L1",
"STAT/APS/H0" "STAT/APS/H0",
"STAT/AFL/LBA",
"STAT/AFH/HBA0",
"STAT/AFH/HBA1"
], ],
"Station_Name": [ "Station_Name": [
"DTS" "DTS"
...@@ -40,13 +42,13 @@ ...@@ -40,13 +42,13 @@
} }
} }
}, },
"EC": { "Calibration": {
"STAT": { "STAT": {
"EC": { "Calibration": {
"STAT/EC/1": { "STAT/Calibration/1": {
"properties": { "properties": {
"OPC_Server_Name": [ "Station_Name": [
"ec-sim.service.consul" "DTS"
] ]
} }
} }
...@@ -68,13 +70,13 @@ ...@@ -68,13 +70,13 @@
} }
} }
}, },
"CCD": { "EC": {
"STAT": { "STAT": {
"CCD": { "EC": {
"STAT/CCD/1": { "STAT/EC/1": {
"properties": { "properties": {
"OPC_Server_Name": [ "OPC_Server_Name": [
"ccd-sim.service.consul" "ec-sim.service.consul"
] ]
} }
} }
...@@ -105,22 +107,22 @@ ...@@ -105,22 +107,22 @@
"00:22:86:08:03:03" "00:22:86:08:03:03"
], ],
"FPGA_beamlet_output_hdr_ip_source_address_RW_default": [ "FPGA_beamlet_output_hdr_ip_source_address_RW_default": [
"192.168.0.1", "10.175.1.1",
"192.168.0.2", "10.175.1.1",
"192.168.0.3", "10.175.1.1",
"192.168.0.4", "10.175.1.1",
"192.168.1.1", "10.175.1.1",
"192.168.1.2", "10.175.1.1",
"192.168.1.3", "10.175.1.1",
"192.168.1.4", "10.175.1.1",
"192.168.2.1", "10.175.1.1",
"192.168.2.2", "10.175.1.1",
"192.168.2.3", "10.175.1.1",
"192.168.2.4", "10.175.1.1",
"192.168.3.1", "10.175.1.1",
"192.168.3.2", "10.175.1.1",
"192.168.3.3", "10.175.1.1",
"192.168.3.4" "10.175.1.1"
], ],
"FPGA_beamlet_output_hdr_udp_source_port_RW_default": [ "FPGA_beamlet_output_hdr_udp_source_port_RW_default": [
"53248", "53248",
...@@ -140,63 +142,30 @@ ...@@ -140,63 +142,30 @@
"53262", "53262",
"53263" "53263"
], ],
"FPGA_beamlet_output_hdr_eth_destination_mac_RW_default": [ "FPGA_beamlet_output_nof_destinations_R_default_shorthand": [
"ec:0d:9a:bf:f2:dc", "4"
"ec:0d:9a:bf:f2:dc", ],
"ec:0d:9a:bf:f2:dc", "FPGA_beamlet_output_multiple_hdr_eth_destination_mac_RW_default_shorthand": [
"ec:0d:9a:bf:f2:dc",
"ec:0d:9a:bf:f2:dc",
"ec:0d:9a:bf:f2:dc",
"ec:0d:9a:bf:f2:dc",
"ec:0d:9a:bf:f2:dc",
"ec:0d:9a:bf:f2:dc",
"ec:0d:9a:bf:f2:dc",
"ec:0d:9a:bf:f2:dc",
"ec:0d:9a:bf:f2:dc",
"ec:0d:9a:bf:f2:dc", "ec:0d:9a:bf:f2:dc",
"ec:0d:9a:bf:f2:dc", "ec:0d:9a:bf:f2:dc",
"ec:0d:9a:bf:f2:dc", "ec:0d:9a:bf:f2:dc",
"ec:0d:9a:bf:f2:dc" "ec:0d:9a:bf:f2:dc"
], ],
"FPGA_beamlet_output_hdr_ip_destination_address_RW_default": [ "FPGA_beamlet_output_multiple_hdr_ip_destination_address_RW_default_shorthand": [
"192.168.1.250",
"192.168.1.250",
"192.168.1.250",
"192.168.1.250",
"192.168.1.250",
"192.168.1.250",
"192.168.1.250",
"192.168.1.250",
"192.168.1.250",
"192.168.1.250",
"192.168.1.250",
"192.168.1.250",
"192.168.1.250", "192.168.1.250",
"192.168.1.250", "192.168.1.250",
"192.168.1.250", "192.168.1.250",
"192.168.1.250" "192.168.1.250"
], ],
"FPGA_beamlet_output_hdr_udp_destination_port_RW_default": [ "FPGA_beamlet_output_multiple_hdr_udp_destination_port_RW_default_shorthand": [
"10001", "10000",
"10001",
"10001",
"10001",
"10001",
"10001", "10001",
"10001", "10002",
"10001", "10003"
"10001",
"10001",
"10001",
"10001",
"10001",
"10001",
"10001",
"10001"
] ]
} }
}, },
"STAT/Beamlet/HBA": { "STAT/Beamlet/HBA0": {
"properties": { "properties": {
"FPGA_beamlet_output_hdr_eth_source_mac_RW_default": [ "FPGA_beamlet_output_hdr_eth_source_mac_RW_default": [
"00:22:86:08:00:00", "00:22:86:08:00:00",
...@@ -217,22 +186,22 @@ ...@@ -217,22 +186,22 @@
"00:22:86:08:03:03" "00:22:86:08:03:03"
], ],
"FPGA_beamlet_output_hdr_ip_source_address_RW_default": [ "FPGA_beamlet_output_hdr_ip_source_address_RW_default": [
"192.168.0.1", "10.175.1.1",
"192.168.0.2", "10.175.1.1",
"192.168.0.3", "10.175.1.1",
"192.168.0.4", "10.175.1.1",
"192.168.1.1", "10.175.1.1",
"192.168.1.2", "10.175.1.1",
"192.168.1.3", "10.175.1.1",
"192.168.1.4", "10.175.1.1",
"192.168.2.1", "10.175.1.1",
"192.168.2.2", "10.175.1.1",
"192.168.2.3", "10.175.1.1",
"192.168.2.4", "10.175.1.1",
"192.168.3.1", "10.175.1.1",
"192.168.3.2", "10.175.1.1",
"192.168.3.3", "10.175.1.1",
"192.168.3.4" "10.175.1.1"
], ],
"FPGA_beamlet_output_hdr_udp_source_port_RW_default": [ "FPGA_beamlet_output_hdr_udp_source_port_RW_default": [
"53248", "53248",
...@@ -252,172 +221,846 @@ ...@@ -252,172 +221,846 @@
"53262", "53262",
"53263" "53263"
], ],
"FPGA_beamlet_output_hdr_eth_destination_mac_RW_default": [ "FPGA_beamlet_output_nof_destinations_R_default_shorthand": [
"ec:0d:9a:bf:f2:dc", "4"
"ec:0d:9a:bf:f2:dc", ],
"ec:0d:9a:bf:f2:dc", "FPGA_beamlet_output_multiple_hdr_eth_destination_mac_RW_default_shorthand": [
"ec:0d:9a:bf:f2:dc",
"ec:0d:9a:bf:f2:dc",
"ec:0d:9a:bf:f2:dc",
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"ec:0d:9a:bf:f2:dc",
"ec:0d:9a:bf:f2:dc",
"ec:0d:9a:bf:f2:dc", "ec:0d:9a:bf:f2:dc",
"ec:0d:9a:bf:f2:dc", "ec:0d:9a:bf:f2:dc",
"ec:0d:9a:bf:f2:dc", "ec:0d:9a:bf:f2:dc",
"ec:0d:9a:bf:f2:dc" "ec:0d:9a:bf:f2:dc"
], ],
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"192.168.1.250",
"192.168.1.250",
"192.168.1.250",
"192.168.1.250",
"192.168.1.250",
"192.168.1.250",
"192.168.1.250",
"192.168.1.250",
"192.168.1.250",
"192.168.1.250", "192.168.1.250",
"192.168.1.250", "192.168.1.250",
"192.168.1.250", "192.168.1.250",
"192.168.1.250"
],
"FPGA_beamlet_output_multiple_hdr_udp_destination_port_RW_default_shorthand": [
"10010",
"10011",
"10012",
"10013"
]
}
},
"STAT/Beamlet/HBA1": {
"properties": {
"FPGA_beamlet_output_hdr_eth_source_mac_RW_default": [
"00:22:86:08:00:00",
"00:22:86:08:00:01",
"00:22:86:08:00:02",
"00:22:86:08:00:03",
"00:22:86:08:01:00",
"00:22:86:08:01:01",
"00:22:86:08:01:02",
"00:22:86:08:01:03",
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"00:22:86:08:03:01",
"00:22:86:08:03:02",
"00:22:86:08:03:03"
],
"FPGA_beamlet_output_hdr_ip_source_address_RW_default": [
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"10.175.1.1",
"10.175.1.1",
"10.175.1.1",
"10.175.1.1",
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],
"FPGA_beamlet_output_hdr_udp_source_port_RW_default": [
"53248",
"53249",
"53250",
"53251",
"53252",
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"53254",
"53255",
"53256",
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"53259",
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"53261",
"53262",
"53263"
],
"FPGA_beamlet_output_nof_destinations_R_default_shorthand": [
"4"
],
"FPGA_beamlet_output_multiple_hdr_eth_destination_mac_RW_default_shorthand": [
"ec:0d:9a:bf:f2:dc",
"ec:0d:9a:bf:f2:dc",
"ec:0d:9a:bf:f2:dc",
"ec:0d:9a:bf:f2:dc"
],
"FPGA_beamlet_output_multiple_hdr_ip_destination_address_RW_default_shorthand": [
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"192.168.1.250", "192.168.1.250",
"192.168.1.250", "192.168.1.250",
"192.168.1.250" "192.168.1.250"
], ],
"FPGA_beamlet_output_hdr_udp_destination_port_RW_default": [ "FPGA_beamlet_output_multiple_hdr_udp_destination_port_RW_default_shorthand": [
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] ]
} }
} }
} }
} }
}, },
"AFH": { "AFL": {
"STAT": { "STAT": {
"AFH": { "AFL": {
"STAT/AFH/HBA": { "STAT/AFL/LBA": {
"properties": { "properties": {
"RECV_Devices": [ "Antenna_Sets": [
"STAT/RECVH/H0" "INNER",
"OUTER",
"SPARSE_EVEN",
"SPARSE_ODD",
"ALL"
],
"Antenna_Set_Masks": [
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], ],
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], ],
"Antenna_Reference_ETRS": [ "Antenna_Cables": [
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} }
...@@ -455,19 +1098,43 @@ ...@@ -455,19 +1098,43 @@
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} }
}, },
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...@@ -479,6 +1146,10 @@ ...@@ -479,6 +1146,10 @@
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} }
...@@ -492,194 +1163,174 @@ ...@@ -492,194 +1163,174 @@
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"0c:c4:7a:c0:30:f1", ],
"0c:c4:7a:c0:30:f1", "FPGA_sdp_info_antenna_field_index_RW_default": [
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"0c:c4:7a:c0:30:f1" "0",
] "0",
} "0",
}, "0",
"STAT/BST/HBA": { "0",
"properties": { "0",
"FPGA_bst_offload_hdr_eth_destination_mac_RW_default": [ "0",
"0c:c4:7a:c0:30:f1", "0",
"0c:c4:7a:c0:30:f1", "0"
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"0c:c4:7a:c0:30:f1"
]
}
}
}
}
},
"SST": {
"STAT": {
"SST": {
"STAT/SST/LBA": {
"properties": {
"FPGA_sst_offload_hdr_eth_destination_mac_RW_default": [
"0c:c4:7a:c0:30:f1",
"0c:c4:7a:c0:30:f1",
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"0c:c4:7a:c0:30:f1"
]
}
},
"STAT/SST/HBA": {
"properties": {
"FPGA_sst_offload_hdr_eth_destination_mac_RW_default": [
"0c:c4:7a:c0:30:f1",
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]
}
}
}
}
},
"XST": {
"STAT": {
"XST": {
"STAT/XST/LBA": {
"properties": {
"FPGA_xst_offload_hdr_eth_destination_mac_RW_default": [
"0c:c4:7a:c0:30:f1",
"0c:c4:7a:c0:30:f1",
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"0c:c4:7a:c0:30:f1"
] ]
} }
}, },
"STAT/XST/HBA": { "STAT/SDP/HBA1": {
"properties": { "properties": {
"FPGA_xst_offload_hdr_eth_destination_mac_RW_default": [ "FPGA_sdp_info_station_id_RW_default": [
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"0c:c4:7a:c0:30:f1" "1"
],
"FPGA_sdp_info_antenna_band_index_RW_default": [
"1",
"1",
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"1",
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],
"FPGA_sdp_info_antenna_field_index_RW_default": [
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"1",
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"1",
"1",
"1",
"1",
"1",
"1",
"1"
] ]
} }
} }
......
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