Skip to content
GitLab
Explore
Sign in
Primary navigation
Search or go to…
Project
T
tango
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Iterations
Wiki
Requirements
Jira issues
Open Jira
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Locked files
Build
Pipelines
Jobs
Pipeline schedules
Test cases
Artifacts
Deploy
Releases
Package registry
Container registry
Model registry
Operate
Environments
Terraform modules
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Code review analytics
Issue analytics
Insights
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
LOFAR2.0
tango
Commits
53968139
Commit
53968139
authored
4 years ago
by
Taya Snijder
Browse files
Options
Downloads
Patches
Plain Diff
added SDP updates
parent
bddd802b
No related branches found
No related tags found
1 merge request
!28
Resolve #2021 "05 10 branched from master sdp update"
Changes
1
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
devices/SDP.py
+36
-33
36 additions, 33 deletions
devices/SDP.py
with
36 additions
and
33 deletions
devices/SDP.py
+
36
−
33
View file @
53968139
...
...
@@ -64,36 +64,40 @@ class SDP(hardware_device):
# ----------
# Attributes
# ----------
fpga_mask_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
1:fpga_mask_RW
"
],
datatype
=
numpy
.
bool_
,
dims
=
(
16
,),
access
=
AttrWriteType
.
READ_WRITE
)
fpga_scrap_R
=
attribute_wrapper
(
comms_annotation
=
[
"
1:fpga_scrap_R
"
],
datatype
=
numpy
.
int32
,
dims
=
(
2048
,))
fpga_scrap_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
1:fpga_scrap_RW
"
],
datatype
=
numpy
.
int32
,
dims
=
(
2048
,),
access
=
AttrWriteType
.
READ_WRITE
)
fpga_status_R
=
attribute_wrapper
(
comms_annotation
=
[
"
1:fpga_status_R
"
],
datatype
=
numpy
.
bool_
,
dims
=
(
16
,))
fpga_temp_R
=
attribute_wrapper
(
comms_annotation
=
[
"
1:fpga_temp_R
"
],
datatype
=
numpy
.
float_
,
dims
=
(
16
,))
fpga_version_R
=
attribute_wrapper
(
comms_annotation
=
[
"
1:fpga_version_R
"
],
datatype
=
numpy
.
str_
,
dims
=
(
16
,))
fpga_weights_R
=
attribute_wrapper
(
comms_annotation
=
[
"
1:fpga_weights_R
"
],
datatype
=
numpy
.
int16
,
dims
=
(
16
,
12
*
488
*
2
))
fpga_weights_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
1:fpga_weights_RW
"
],
datatype
=
numpy
.
int16
,
dims
=
(
16
,
12
*
488
*
2
),
access
=
AttrWriteType
.
READ_WRITE
)
fpga_processing_enable_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
1:fpga_processing_enable_RW
"
],
datatype
=
numpy
.
bool_
,
dims
=
(
16
,),
access
=
AttrWriteType
.
READ_WRITE
)
fpga_processing_enable_R
=
attribute_wrapper
(
comms_annotation
=
[
"
1:fpga_processing_enable_R
"
],
datatype
=
numpy
.
bool_
,
dims
=
(
16
,))
fpga_sst_offload_enable_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
1:fpga_sst_offload_enable_RW
"
],
datatype
=
numpy
.
bool_
,
dims
=
(
16
,),
access
=
AttrWriteType
.
READ_WRITE
)
fpga_sst_offload_enable_R
=
attribute_wrapper
(
comms_annotation
=
[
"
1:fpga_sst_offload_enable_R
"
],
datatype
=
numpy
.
bool_
,
dims
=
(
16
,))
fpga_sst_offload_dest_mac_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
1:fpga_sst_offload_dest_mac_RW
"
],
datatype
=
numpy
.
str_
,
dims
=
(
16
,),
access
=
AttrWriteType
.
READ_WRITE
)
fpga_sst_offload_dest_mac_R
=
attribute_wrapper
(
comms_annotation
=
[
"
1:fpga_sst_offload_dest_mac_R
"
],
datatype
=
numpy
.
str_
,
dims
=
(
16
,))
fpga_sst_offload_dest_ip_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
1:fpga_sst_offload_dest_ip_RW
"
],
datatype
=
numpy
.
str_
,
dims
=
(
16
,),
access
=
AttrWriteType
.
READ_WRITE
)
fpga_sst_offload_dest_ip_R
=
attribute_wrapper
(
comms_annotation
=
[
"
1:fpga_sst_offload_dest_ip_R
"
],
datatype
=
numpy
.
str_
,
dims
=
(
16
,))
fpga_sst_offload_dest_port_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
1:fpga_sst_offload_dest_port_RW
"
],
datatype
=
numpy
.
uint16
,
dims
=
(
16
,),
access
=
AttrWriteType
.
READ_WRITE
)
fpga_sst_offload_dest_port_R
=
attribute_wrapper
(
comms_annotation
=
[
"
1:fpga_sst_offload_dest_port_R
"
],
datatype
=
numpy
.
uint16
,
dims
=
(
16
,))
fpga_sdp_info_station_id_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
1:fpga_sdp_info_station_id_RW
"
],
datatype
=
numpy
.
uint16
,
dims
=
(
16
,),
access
=
AttrWriteType
.
READ_WRITE
)
fpga_sdp_info_station_id_R
=
attribute_wrapper
(
comms_annotation
=
[
"
1:fpga_sdp_info_station_id_R
"
],
datatype
=
numpy
.
uint16
,
dims
=
(
16
,))
fpga_sdp_info_observation_id_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
1:fpga_sdp_info_observation_id_RW
"
],
datatype
=
numpy
.
uint32
,
dims
=
(
16
,),
access
=
AttrWriteType
.
READ_WRITE
)
fpga_sdp_info_observation_id_R
=
attribute_wrapper
(
comms_annotation
=
[
"
1:fpga_sdp_info_observation_id_R
"
],
datatype
=
numpy
.
uint32
,
dims
=
(
16
,))
fpga_sdp_info_source_id_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
1:fpga_sdp_info_source_id_RW
"
],
datatype
=
numpy
.
uint16
,
dims
=
(
16
,),
access
=
AttrWriteType
.
READ_WRITE
)
fpga_sdp_info_source_id_R
=
attribute_wrapper
(
comms_annotation
=
[
"
1:fpga_sdp_info_source_id_R
"
],
datatype
=
numpy
.
uint16
,
dims
=
(
16
,))
tr_busy_R
=
attribute_wrapper
(
comms_annotation
=
[
"
1:tr_busy_R
"
],
datatype
=
numpy
.
bool_
)
# NOTE: typo in node name is 'tr_reload_W' should be 'tr_reload_RW'
tr_reload_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
1:tr_reload_W
"
],
datatype
=
numpy
.
bool_
,
access
=
AttrWriteType
.
READ_WRITE
)
tr_tod_R
=
attribute_wrapper
(
comms_annotation
=
[
"
1:tr_tod_R
"
],
datatype
=
numpy
.
uint64
)
tr_uptime_R
=
attribute_wrapper
(
comms_annotation
=
[
"
1:tr_uptime_R
"
],
datatype
=
numpy
.
uint64
)
fpga_mask_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
2:fpga_mask_RW
"
],
datatype
=
numpy
.
bool_
,
dims
=
(
16
,),
access
=
AttrWriteType
.
READ_WRITE
)
fpga_scrap_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:fpga_scrap_R
"
],
datatype
=
numpy
.
int32
,
dims
=
(
2048
,))
fpga_scrap_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
2:fpga_scrap_RW
"
],
datatype
=
numpy
.
int32
,
dims
=
(
2048
,),
access
=
AttrWriteType
.
READ_WRITE
)
fpga_status_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:fpga_status_R
"
],
datatype
=
numpy
.
bool_
,
dims
=
(
16
,))
fpga_temp_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:fpga_temp_R
"
],
datatype
=
numpy
.
float_
,
dims
=
(
16
,))
fpga_version_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:fpga_version_R
"
],
datatype
=
numpy
.
str_
,
dims
=
(
16
,))
fpga_weights_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:fpga_weights_R
"
],
datatype
=
numpy
.
int16
,
dims
=
(
16
,
12
*
488
*
2
))
fpga_weights_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
2:fpga_weights_RW
"
],
datatype
=
numpy
.
int16
,
dims
=
(
16
,
12
*
488
*
2
),
access
=
AttrWriteType
.
READ_WRITE
)
fpga_processing_enable_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
2:fpga_processing_enable_RW
"
],
datatype
=
numpy
.
bool_
,
dims
=
(
16
,),
access
=
AttrWriteType
.
READ_WRITE
)
fpga_processing_enable_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:fpga_processing_enable_R
"
],
datatype
=
numpy
.
bool_
,
dims
=
(
16
,))
fpga_sst_offload_enable_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
2:fpga_sst_offload_enable_RW
"
],
datatype
=
numpy
.
bool_
,
dims
=
(
16
,),
access
=
AttrWriteType
.
READ_WRITE
)
fpga_sst_offload_enable_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:fpga_sst_offload_enable_R
"
],
datatype
=
numpy
.
bool_
,
dims
=
(
16
,))
fpga_sst_offload_dest_mac_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
2:fpga_sst_offload_dest_mac_RW
"
],
datatype
=
numpy
.
str_
,
dims
=
(
16
,),
access
=
AttrWriteType
.
READ_WRITE
)
fpga_sst_offload_dest_mac_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:fpga_sst_offload_dest_mac_R
"
],
datatype
=
numpy
.
str_
,
dims
=
(
16
,))
fpga_sst_offload_dest_ip_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
2:fpga_sst_offload_dest_ip_RW
"
],
datatype
=
numpy
.
str_
,
dims
=
(
16
,),
access
=
AttrWriteType
.
READ_WRITE
)
fpga_sst_offload_dest_ip_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:fpga_sst_offload_dest_ip_R
"
],
datatype
=
numpy
.
str_
,
dims
=
(
16
,))
fpga_sst_offload_dest_port_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
2:fpga_sst_offload_dest_port_RW
"
],
datatype
=
numpy
.
uint16
,
dims
=
(
16
,),
access
=
AttrWriteType
.
READ_WRITE
)
fpga_sst_offload_dest_port_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:fpga_sst_offload_dest_port_R
"
],
datatype
=
numpy
.
uint16
,
dims
=
(
16
,))
fpga_sdp_info_station_id_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
2:fpga_sdp_info_station_id_RW
"
],
datatype
=
numpy
.
uint16
,
dims
=
(
16
,),
access
=
AttrWriteType
.
READ_WRITE
)
fpga_sdp_info_station_id_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:fpga_sdp_info_station_id_R
"
],
datatype
=
numpy
.
uint16
,
dims
=
(
16
,))
fpga_sdp_info_observation_id_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
2:fpga_sdp_info_observation_id_RW
"
],
datatype
=
numpy
.
uint32
,
dims
=
(
16
,),
access
=
AttrWriteType
.
READ_WRITE
)
fpga_sdp_info_observation_id_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:fpga_sdp_info_observation_id_R
"
],
datatype
=
numpy
.
uint32
,
dims
=
(
16
,))
fpga_sdp_info_source_id_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
2:fpga_sdp_info_source_id_RW
"
],
datatype
=
numpy
.
uint16
,
dims
=
(
16
,),
access
=
AttrWriteType
.
READ_WRITE
)
fpga_sdp_info_source_id_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:fpga_sdp_info_source_id_R
"
],
datatype
=
numpy
.
uint16
,
dims
=
(
16
,))
tr_busy_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:tr_busy_R
"
],
datatype
=
numpy
.
bool_
)
tr_reload_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
2:tr_reload_RW
"
],
datatype
=
numpy
.
bool_
,
access
=
AttrWriteType
.
READ_WRITE
)
tr_tod_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:tr_tod_R
"
],
datatype
=
numpy
.
uint64
)
tr_uptime_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:tr_uptime_R
"
],
datatype
=
numpy
.
uint64
)
FPGA_firmware_version_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:FPGA_firmware_version_R
"
],
datatype
=
numpy
.
str_
,
dims
=
(
16
,))
FPGA_hardware_version_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:FPGA_hardware_version_R
"
],
datatype
=
numpy
.
str_
,
dims
=
(
16
,))
tr_software_version_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:tr_software_version_R
"
],
datatype
=
numpy
.
str_
)
def
always_executed_hook
(
self
):
"""
Method always executed before any TANGO command is executed.
"""
...
...
@@ -116,14 +120,14 @@ class SDP(hardware_device):
# overloaded functions
# --------
@log_exceptions
()
def
off
(
self
):
def
configure_for_
off
(
self
):
"""
user code here. is called when the state is set to OFF
"""
# Stop keep-alive
self
.
opcua_connection
.
stop
()
@log_exceptions
()
def
initialise
(
self
):
def
configure_for_
initialise
(
self
):
"""
user code here. is called when the sate is set to INIT
"""
"""
Initialises the attributes and properties of the SDP.
"""
...
...
@@ -150,4 +154,3 @@ def main(args=None, **kwargs):
if
__name__
==
'
__main__
'
:
main
()
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment