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LOFAR2.0
tango
Commits
393b6dc5
Commit
393b6dc5
authored
Sep 28, 2021
by
Jan David Mol
Browse files
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Plain Diff
L2SS-357
: UNB2 attributes are still under 2:PCC
parent
25e9b695
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devices/devices/unb2.py
+68
-68
68 additions, 68 deletions
devices/devices/unb2.py
with
68 additions
and
68 deletions
devices/devices/unb2.py
+
68
−
68
View file @
393b6dc5
...
...
@@ -87,81 +87,81 @@ class UNB2(hardware_device):
##XXX Means Under discussion
# Special case for the on off switch: instead of UNB2_Power_ON_OFF_R we use UNB2_POL_FPGA_CORE_VOUT_R as the MP
UNB2_Power_ON_OFF_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_Power_ON_OFF_RW
"
],
datatype
=
numpy
.
bool_
,
dims
=
(
N_unb
,),
access
=
AttrWriteType
.
READ_WRITE
)
UNB2_Front_Panel_LED_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_Front_Panel_LED_RW
"
],
datatype
=
numpy
.
uint8
,
dims
=
(
N_unb
,),
access
=
AttrWriteType
.
READ_WRITE
)
UNB2_Front_Panel_LED_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_Front_Panel_LED_R
"
],
datatype
=
numpy
.
uint8
,
dims
=
(
N_unb
,))
UNB2_mask_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_mask_RW
"
],
datatype
=
numpy
.
bool_
,
dims
=
(
N_unb
,),
access
=
AttrWriteType
.
READ_WRITE
)
UNB2_Power_ON_OFF_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_Power_ON_OFF_RW
"
],
datatype
=
numpy
.
bool_
,
dims
=
(
N_unb
,),
access
=
AttrWriteType
.
READ_WRITE
)
UNB2_Front_Panel_LED_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_Front_Panel_LED_RW
"
],
datatype
=
numpy
.
uint8
,
dims
=
(
N_unb
,),
access
=
AttrWriteType
.
READ_WRITE
)
UNB2_Front_Panel_LED_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_Front_Panel_LED_R
"
],
datatype
=
numpy
.
uint8
,
dims
=
(
N_unb
,))
UNB2_mask_RW
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_mask_RW
"
],
datatype
=
numpy
.
bool_
,
dims
=
(
N_unb
,),
access
=
AttrWriteType
.
READ_WRITE
)
# Not yet deployed
#UNB2_mask_R = attribute_wrapper(comms_annotation=["2:
RECV
", "2:UNB2_mask_R"], datatype=numpy.bool_, dims=(N_unb,))
#UNB2_mask_R = attribute_wrapper(comms_annotation=["2:
PCC
", "2:UNB2_mask_R"], datatype=numpy.bool_, dims=(N_unb,))
### Central MP per Uniboard
# These three are only available in UNB2c
UNB2_I2C_bus_STATUS_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_I2C_bus_STATUS_R
"
],
datatype
=
numpy
.
bool_
,
dims
=
(
N_unb
,))
UNB2_I2C_bus_STATUS_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_I2C_bus_STATUS_R
"
],
datatype
=
numpy
.
bool_
,
dims
=
(
N_unb
,))
##UNB2_I2C_bus_STATUS_R will probably be renamed to UNB2_I2C_bus_OK_R
##UNB2_I2C_bus_OK_R = attribute_wrapper(comms_annotation=["2:
RECV
", "2:UNB2_I2C_bus_OK_R"], datatype=numpy.bool_, dims=(N_unb,))
#UNB2_EEPROM_Serial_Number_R = attribute_wrapper(comms_annotation=["2:
RECV
", "2:UNB2_EEPROM_Serial_Number_R"], datatype=numpy.str, dims=(N_unb,))
UNB2_EEPROM_Unique_ID_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_EEPROM_Unique_ID_R
"
],
datatype
=
numpy
.
uint32
,
dims
=
(
N_unb
,))
UNB2_DC_DC_48V_12V_VIN_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_DC_DC_48V_12V_VIN_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_DC_DC_48V_12V_VOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_DC_DC_48V_12V_VOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_DC_DC_48V_12V_IOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_DC_DC_48V_12V_IOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_DC_DC_48V_12V_TEMP_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_DC_DC_48V_12V_TEMP_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_QSFP_N01_VOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_POL_QSFP_N01_VOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_QSFP_N01_IOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_POL_QSFP_N01_IOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_QSFP_N01_TEMP_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_POL_QSFP_N01_TEMP_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_QSFP_N23_VOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_POL_QSFP_N23_VOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_QSFP_N23_IOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_POL_QSFP_N23_IOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_QSFP_N23_TEMP_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_POL_QSFP_N23_TEMP_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_SWITCH_1V2_VOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_POL_SWITCH_1V2_VOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_SWITCH_1V2_IOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_POL_SWITCH_1V2_IOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_SWITCH_1V2_TEMP_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_POL_SWITCH_1V2_TEMP_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_SWITCH_PHY_VOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_POL_SWITCH_PHY_VOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_SWITCH_PHY_IOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_POL_SWITCH_PHY_IOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_SWITCH_PHY_TEMP_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_POL_SWITCH_PHY_TEMP_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_CLOCK_VOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_POL_CLOCK_VOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_CLOCK_IOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_POL_CLOCK_IOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_CLOCK_TEMP_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_POL_CLOCK_TEMP_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
##UNB2_I2C_bus_OK_R = attribute_wrapper(comms_annotation=["2:
PCC
", "2:UNB2_I2C_bus_OK_R"], datatype=numpy.bool_, dims=(N_unb,))
#UNB2_EEPROM_Serial_Number_R = attribute_wrapper(comms_annotation=["2:
PCC
", "2:UNB2_EEPROM_Serial_Number_R"], datatype=numpy.str, dims=(N_unb,))
UNB2_EEPROM_Unique_ID_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_EEPROM_Unique_ID_R
"
],
datatype
=
numpy
.
uint32
,
dims
=
(
N_unb
,))
UNB2_DC_DC_48V_12V_VIN_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_DC_DC_48V_12V_VIN_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_DC_DC_48V_12V_VOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_DC_DC_48V_12V_VOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_DC_DC_48V_12V_IOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_DC_DC_48V_12V_IOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_DC_DC_48V_12V_TEMP_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_DC_DC_48V_12V_TEMP_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_QSFP_N01_VOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_POL_QSFP_N01_VOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_QSFP_N01_IOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_POL_QSFP_N01_IOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_QSFP_N01_TEMP_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_POL_QSFP_N01_TEMP_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_QSFP_N23_VOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_POL_QSFP_N23_VOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_QSFP_N23_IOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_POL_QSFP_N23_IOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_QSFP_N23_TEMP_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_POL_QSFP_N23_TEMP_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_SWITCH_1V2_VOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_POL_SWITCH_1V2_VOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_SWITCH_1V2_IOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_POL_SWITCH_1V2_IOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_SWITCH_1V2_TEMP_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_POL_SWITCH_1V2_TEMP_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_SWITCH_PHY_VOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_POL_SWITCH_PHY_VOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_SWITCH_PHY_IOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_POL_SWITCH_PHY_IOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_SWITCH_PHY_TEMP_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_POL_SWITCH_PHY_TEMP_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_CLOCK_VOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_POL_CLOCK_VOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_CLOCK_IOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_POL_CLOCK_IOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
UNB2_POL_CLOCK_TEMP_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_POL_CLOCK_TEMP_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_unb
,))
### Local MP per FPGA
UNB2_FPGA_DDR4_SLOT_TEMP_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_FPGA_DDR4_SLOT_TEMP_R
"
],
datatype
=
numpy
.
double
,
dims
=
((
N_fpga
*
N_ddr
),
N_unb
))
#UNB2_FPGA_DDR4_SLOT_PART_NUMBER_R = attribute_wrapper(comms_annotation=["2:
RECV
", "2:UNB2_FPGA_DDR4_SLOT_PART_NUMBER_R"], datatype=numpy.str, dims=(N_fpga * N_ddr), N_unb))
#UNB2_FPGA_QSFP_CAGE_TEMP_R = attribute_wrapper(comms_annotation=["2:
RECV
", "2:UNB2_FPGA_QSFP_CAGE_0_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_1_TEMP_R = attribute_wrapper(comms_annotation=["2:
RECV
", "2:UNB2_FPGA_QSFP_CAGE_1_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_2_TEMP_R = attribute_wrapper(comms_annotation=["2:
RECV
", "2:UNB2_FPGA_QSFP_CAGE_2_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_3_TEMP_R = attribute_wrapper(comms_annotation=["2:
RECV
", "2:UNB2_FPGA_QSFP_CAGE_3_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_4_TEMP_R = attribute_wrapper(comms_annotation=["2:
RECV
", "2:UNB2_FPGA_QSFP_CAGE_4_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_5_TEMP_R = attribute_wrapper(comms_annotation=["2:
RECV
", "2:UNB2_FPGA_QSFP_CAGE_5_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_LOS_R = attribute_wrapper(comms_annotation=["2:
RECV
", "2:UNB2_FPGA_QSFP_CAGE_0_LOS_R"], datatype=numpy.uint8, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_1_LOS_R = attribute_wrapper(comms_annotation=["2:
RECV
", "2:UNB2_FPGA_QSFP_CAGE_1_LOS_R"], datatype=numpy.uint8, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_2_LOS_R = attribute_wrapper(comms_annotation=["2:
RECV
", "2:UNB2_FPGA_QSFP_CAGE_2_LOS_R"], datatype=numpy.uint8, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_3_LOS_R = attribute_wrapper(comms_annotation=["2:
RECV
", "2:UNB2_FPGA_QSFP_CAGE_3_LOS_R"], datatype=numpy.uint8, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_4_LOS_R = attribute_wrapper(comms_annotation=["2:
RECV
", "2:UNB2_FPGA_QSFP_CAGE_4_LOS_R"], datatype=numpy.uint8, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_5_LOS_R = attribute_wrapper(comms_annotation=["2:
RECV
", "2:UNB2_FPGA_QSFP_CAGE_5_LOS_R"], datatype=numpy.uint8, dims=(N_fpga, N_unb))
#UNB2_FPGA_POL_CORE_VOUT_R = attribute_wrapper(comms_annotation=["2:
RECV
", "2:UNB2_POL_FPGA_CORE_VOUT_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_CORE_IOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_FPGA_POL_CORE_IOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_CORE_TEMP_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_FPGA_POL_CORE_TEMP_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_ERAM_VOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_FPGA_POL_ERAM_VOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_ERAM_IOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_FPGA_POL_ERAM_IOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_ERAM_TEMP_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_FPGA_POL_ERAM_TEMP_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_RXGXB_VOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_FPGA_POL_RXGXB_VOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_RXGXB_IOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_FPGA_POL_RXGXB_IOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_RXGXB_TEMP_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_FPGA_POL_RXGXB_TEMP_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_TXGXB_VOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_FPGA_POL_TXGXB_VOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_TXGXB_IOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_FPGA_POL_TXGXB_IOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
#UNB2_FPGA_POL_TXGXB_TEMP_R = attribute_wrapper(comms_annotation=["2:
RECV
", "2:UNB2_POL_FPGA_TXGXB_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_HGXB_VOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_FPGA_POL_HGXB_VOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_HGXB_IOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_FPGA_POL_HGXB_IOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_HGXB_TEMP_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_FPGA_POL_HGXB_TEMP_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_PGM_VOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_FPGA_POL_PGM_VOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_PGM_IOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_FPGA_POL_PGM_IOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_PGM_TEMP_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
RECV
"
,
"
2:UNB2_FPGA_POL_PGM_TEMP_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
##UNB2_I2C_bus_QSFP_STATUS_R = attribute_wrapper(comms_annotation=["2:
RECV
", "2:UNB2_I2C_bus_QSFP_STATUS_R"], datatype=numpy.int64, dims=((N_unb * N_fpga), N_qsfp))
##UNB2_I2C_bus_DDR4_STATUS_R = attribute_wrapper(comms_annotation=["2:
RECV
", "2:UNB2_I2C_bus_DDR4_STATUS_R"], datatype=numpy.int64, dims=(N_ddr, N_fpga))
##UNB2_I2C_bus_FPGA_PS_STATUS_R = attribute_wrapper(comms_annotation=["2:
RECV
", "2:UNB2_I2C_bus_FPGA_PS_STATUS_R"], datatype=numpy.int64, dims=(N_unb * N_fpga,))
##UNB2_I2C_bus_PS_STATUS_R = attribute_wrapper(comms_annotation=["2:
RECV
", "2:UNB2_I2C_bus_PS_STATUS_R"], datatype=numpy.double, dims=(N_unb,))
##UNB2_translator_busy_R = attribute_wrapper(comms_annotation=["2:
RECV
", "2:UNB2_translator_busy_R"], datatype=numpy.bool_)
##UNB2_monitor_rate_RW = attribute_wrapper(comms_annotation=["2:
RECV
", "2:UNB2_monitor_rate_RW"], datatype=numpy.double, dims=(N_unb,), access=AttrWriteType.READ_WRITE)
UNB2_FPGA_DDR4_SLOT_TEMP_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_FPGA_DDR4_SLOT_TEMP_R
"
],
datatype
=
numpy
.
double
,
dims
=
((
N_fpga
*
N_ddr
),
N_unb
))
#UNB2_FPGA_DDR4_SLOT_PART_NUMBER_R = attribute_wrapper(comms_annotation=["2:
PCC
", "2:UNB2_FPGA_DDR4_SLOT_PART_NUMBER_R"], datatype=numpy.str, dims=(N_fpga * N_ddr), N_unb))
#UNB2_FPGA_QSFP_CAGE_TEMP_R = attribute_wrapper(comms_annotation=["2:
PCC
", "2:UNB2_FPGA_QSFP_CAGE_0_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_1_TEMP_R = attribute_wrapper(comms_annotation=["2:
PCC
", "2:UNB2_FPGA_QSFP_CAGE_1_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_2_TEMP_R = attribute_wrapper(comms_annotation=["2:
PCC
", "2:UNB2_FPGA_QSFP_CAGE_2_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_3_TEMP_R = attribute_wrapper(comms_annotation=["2:
PCC
", "2:UNB2_FPGA_QSFP_CAGE_3_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_4_TEMP_R = attribute_wrapper(comms_annotation=["2:
PCC
", "2:UNB2_FPGA_QSFP_CAGE_4_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_5_TEMP_R = attribute_wrapper(comms_annotation=["2:
PCC
", "2:UNB2_FPGA_QSFP_CAGE_5_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_LOS_R = attribute_wrapper(comms_annotation=["2:
PCC
", "2:UNB2_FPGA_QSFP_CAGE_0_LOS_R"], datatype=numpy.uint8, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_1_LOS_R = attribute_wrapper(comms_annotation=["2:
PCC
", "2:UNB2_FPGA_QSFP_CAGE_1_LOS_R"], datatype=numpy.uint8, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_2_LOS_R = attribute_wrapper(comms_annotation=["2:
PCC
", "2:UNB2_FPGA_QSFP_CAGE_2_LOS_R"], datatype=numpy.uint8, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_3_LOS_R = attribute_wrapper(comms_annotation=["2:
PCC
", "2:UNB2_FPGA_QSFP_CAGE_3_LOS_R"], datatype=numpy.uint8, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_4_LOS_R = attribute_wrapper(comms_annotation=["2:
PCC
", "2:UNB2_FPGA_QSFP_CAGE_4_LOS_R"], datatype=numpy.uint8, dims=(N_fpga, N_unb))
#UNB2_FPGA_QSFP_CAGE_5_LOS_R = attribute_wrapper(comms_annotation=["2:
PCC
", "2:UNB2_FPGA_QSFP_CAGE_5_LOS_R"], datatype=numpy.uint8, dims=(N_fpga, N_unb))
#UNB2_FPGA_POL_CORE_VOUT_R = attribute_wrapper(comms_annotation=["2:
PCC
", "2:UNB2_POL_FPGA_CORE_VOUT_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_CORE_IOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_FPGA_POL_CORE_IOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_CORE_TEMP_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_FPGA_POL_CORE_TEMP_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_ERAM_VOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_FPGA_POL_ERAM_VOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_ERAM_IOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_FPGA_POL_ERAM_IOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_ERAM_TEMP_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_FPGA_POL_ERAM_TEMP_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_RXGXB_VOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_FPGA_POL_RXGXB_VOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_RXGXB_IOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_FPGA_POL_RXGXB_IOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_RXGXB_TEMP_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_FPGA_POL_RXGXB_TEMP_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_TXGXB_VOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_FPGA_POL_TXGXB_VOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_TXGXB_IOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_FPGA_POL_TXGXB_IOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
#UNB2_FPGA_POL_TXGXB_TEMP_R = attribute_wrapper(comms_annotation=["2:
PCC
", "2:UNB2_POL_FPGA_TXGXB_TEMP_R"], datatype=numpy.double, dims=(N_fpga, N_unb))
UNB2_FPGA_POL_HGXB_VOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_FPGA_POL_HGXB_VOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_HGXB_IOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_FPGA_POL_HGXB_IOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_HGXB_TEMP_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_FPGA_POL_HGXB_TEMP_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_PGM_VOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_FPGA_POL_PGM_VOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_PGM_IOUT_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_FPGA_POL_PGM_IOUT_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
UNB2_FPGA_POL_PGM_TEMP_R
=
attribute_wrapper
(
comms_annotation
=
[
"
2:
PCC
"
,
"
2:UNB2_FPGA_POL_PGM_TEMP_R
"
],
datatype
=
numpy
.
double
,
dims
=
(
N_fpga
,
N_unb
))
##UNB2_I2C_bus_QSFP_STATUS_R = attribute_wrapper(comms_annotation=["2:
PCC
", "2:UNB2_I2C_bus_QSFP_STATUS_R"], datatype=numpy.int64, dims=((N_unb * N_fpga), N_qsfp))
##UNB2_I2C_bus_DDR4_STATUS_R = attribute_wrapper(comms_annotation=["2:
PCC
", "2:UNB2_I2C_bus_DDR4_STATUS_R"], datatype=numpy.int64, dims=(N_ddr, N_fpga))
##UNB2_I2C_bus_FPGA_PS_STATUS_R = attribute_wrapper(comms_annotation=["2:
PCC
", "2:UNB2_I2C_bus_FPGA_PS_STATUS_R"], datatype=numpy.int64, dims=(N_unb * N_fpga,))
##UNB2_I2C_bus_PS_STATUS_R = attribute_wrapper(comms_annotation=["2:
PCC
", "2:UNB2_I2C_bus_PS_STATUS_R"], datatype=numpy.double, dims=(N_unb,))
##UNB2_translator_busy_R = attribute_wrapper(comms_annotation=["2:
PCC
", "2:UNB2_translator_busy_R"], datatype=numpy.bool_)
##UNB2_monitor_rate_RW = attribute_wrapper(comms_annotation=["2:
PCC
", "2:UNB2_monitor_rate_RW"], datatype=numpy.double, dims=(N_unb,), access=AttrWriteType.READ_WRITE)
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