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Commit 125eee4d authored by Taya Snijder's avatar Taya Snijder
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fixed constant use

parent a652628d
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1 merge request!465added constants.py and replaced most magic numbers
...@@ -195,8 +195,8 @@ class SDP(opcua_device): ...@@ -195,8 +195,8 @@ class SDP(opcua_device):
value = numpy.array(value) value = numpy.array(value)
# validate shape # validate shape
if value.shape != (self.N_pn, self.S_pn): if value.shape != (N_pn, S_pn):
raise ValueError(f"Dimension mismatch. Expected ({self.N_pn}, {self.S_pn}), got {value.shape}.") raise ValueError(f"Dimension mismatch. Expected ({N_pn}, {S_pn}), got {value.shape}.")
# validate content # validate content
for val in value.flatten(): for val in value.flatten():
...@@ -249,7 +249,7 @@ class SDP(opcua_device): ...@@ -249,7 +249,7 @@ class SDP(opcua_device):
raise ValueError(f"Unsupported clock frequency: {clock}") raise ValueError(f"Unsupported clock frequency: {clock}")
# Tell all FPGAs to use this clock # Tell all FPGAs to use this clock
self.proxy.FPGA_pps_expected_cnt_RW = [clock] * self.N_pn self.proxy.FPGA_pps_expected_cnt_RW = [clock] * N_pn
# Also update the packet headers. We assume the first Nyquist zone of each FPGA is representative # Also update the packet headers. We assume the first Nyquist zone of each FPGA is representative
self.proxy.FPGA_sdp_info_nyquist_sampling_zone_index_RW = self._nyquist_zone(clock)[:,0] self.proxy.FPGA_sdp_info_nyquist_sampling_zone_index_RW = self._nyquist_zone(clock)[:,0]
...@@ -291,7 +291,7 @@ class SDP(opcua_device): ...@@ -291,7 +291,7 @@ class SDP(opcua_device):
# Store which type of antenna is connected to each input. # Store which type of antenna is connected to each input.
# #
# We need to be told this by AntennaField, through configure_for_antennafield. # We need to be told this by AntennaField, through configure_for_antennafield.
self._antenna_type = numpy.array([["LBA"] * self.S_pn] * self.N_pn, dtype=str) self._antenna_type = numpy.array([["LBA"] * S_pn] * N_pn, dtype=str)
def _prepare_hardware(self): def _prepare_hardware(self):
# FPGAs that are actually reachable and we care about # FPGAs that are actually reachable and we care about
......
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