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unb1_ddr3.vhd 13.50 KiB
-------------------------------------------------------------------------------
--
-- Copyright (C) 2011
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, technology_lib, tech_ddr_lib, io_ddr_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY unb1_ddr3 IS
GENERIC (
g_sim : BOOLEAN := FALSE;
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 4;
-- Stamps are passed via QIP at compile start if $UNB_COMPILE_STAMPS is set
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD)
g_stamp_time : NATURAL := 0; -- Time (HHMMSS)
g_stamp_svn : NATURAL := 0; -- SVN revision
g_st_dat_w : NATURAL := 64 -- Any power of two 8..256
);
PORT (
-- GENERAL
CLK : IN STD_LOGIC; -- System Clock
PPS : IN STD_LOGIC; -- System Sync
WDI : OUT STD_LOGIC; -- Watchdog Clear
INTA : INOUT STD_LOGIC; -- FPGA interconnect line
INTB : INOUT STD_LOGIC; -- FPGA interconnect line
-- Others
VERSION : IN STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
TESTIO : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
-- I2C Interface to Sensors
sens_sc : INOUT STD_LOGIC;
sens_sd : INOUT STD_LOGIC;
-- 1GbE Control Interface
ETH_clk : IN STD_LOGIC;
ETH_SGIN : IN STD_LOGIC;
ETH_SGOUT : OUT STD_LOGIC;
-- SO-DIMM Memory Bank I
MB_I_IN : IN t_tech_ddr3_phy_in;
MB_I_IO : INOUT t_tech_ddr3_phy_io;
MB_I_OU : OUT t_tech_ddr3_phy_ou
);END unb1_ddr3;
ARCHITECTURE str OF unb1_ddr3 IS
-- Constant definitions for ctrl_unb_common
CONSTANT c_design_name : STRING := "unb1_ddr3";
CONSTANT c_design_note : STRING := "DDR3 reference design";
CONSTANT c_fw_version : t_unb1_board_fw_version := (0, 3); -- firmware version x.y
-- Use PHY Interface
-- TYPE t_c_unb_use_phy IS RECORD
-- eth1g : NATURAL;
-- tr_front: NATURAL;
-- tr_mesh : NATURAL;
-- tr_back : NATURAL;
-- ddr3_I : NATURAL;
-- ddr3_II : NATURAL;
-- adc : NATURAL;
-- wdi : NATURAL;
-- END RECORD;
CONSTANT c_use_phy : t_c_unb1_board_use_phy := (1, 0, 0, 0, 1, 0, 0, 1);
CONSTANT c_aux : t_c_unb1_board_aux := c_unb1_board_aux;
CONSTANT c_app_led_en : BOOLEAN := TRUE;
CONSTANT c_technology : NATURAL := c_tech_select_default;
CONSTANT c_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
-- System
SIGNAL cs_sim : STD_LOGIC;
SIGNAL xo_clk : STD_LOGIC;
SIGNAL xo_rst : STD_LOGIC;
SIGNAL xo_rst_n : STD_LOGIC;
SIGNAL cal_clk : STD_LOGIC;
SIGNAL mm_clk : STD_LOGIC;
SIGNAL mm_locked : STD_LOGIC;
SIGNAL mm_rst : STD_LOGIC;
SIGNAL dp_rst : STD_LOGIC;
SIGNAL dp_clk : STD_LOGIC;
SIGNAL dp_pps : STD_LOGIC;
SIGNAL ddr_ref_rst : STD_LOGIC;
SIGNAL this_chip_id : STD_LOGIC_VECTOR(c_unb1_board_nof_chip_w-1 DOWNTO 0); -- [2:0], so range 0-3 for FN and range 4-7 BN
SIGNAL app_led_red : STD_LOGIC := '0';
SIGNAL app_led_green : STD_LOGIC := '1';
-- PIOs
SIGNAL pout_debug_wave : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
SIGNAL pout_wdi : STD_LOGIC;
-- WDI override
SIGNAL reg_wdi_mosi : t_mem_mosi;
SIGNAL reg_wdi_miso : t_mem_miso;
-- PPSH
SIGNAL reg_ppsh_mosi : t_mem_mosi;
SIGNAL reg_ppsh_miso : t_mem_miso;
-- UniBoard system info
SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
SIGNAL reg_unb_system_info_miso : t_mem_miso;
SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
SIGNAL rom_unb_system_info_miso : t_mem_miso;
-- eth1g
SIGNAL eth1g_tse_clk : STD_LOGIC;
SIGNAL eth1g_mm_rst : STD_LOGIC;
SIGNAL eth1g_tse_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH TSE MAC registers
SIGNAL eth1g_tse_miso : t_mem_miso; SIGNAL eth1g_reg_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH control and status registers
SIGNAL eth1g_reg_miso : t_mem_miso;
SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
SIGNAL eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH rx frame and tx frame memory
SIGNAL eth1g_ram_miso : t_mem_miso;
-- SIGNAL eth1g_led : t_tech_tse_led;
-- . UniBoard I2C sens
SIGNAL reg_unb_sens_mosi : t_mem_mosi;
SIGNAL reg_unb_sens_miso : t_mem_miso;
-- IO DDR register map
SIGNAL reg_io_ddr_mosi : t_mem_mosi;
SIGNAL reg_io_ddr_miso : t_mem_miso;
-- MM registers
SIGNAL reg_diagnostics_mosi : t_mem_mosi;
SIGNAL reg_diagnostics_miso : t_mem_miso;
BEGIN
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
u_ctrl : ENTITY unb1_board_lib.ctrl_unb1_board
GENERIC MAP (
-- General
g_sim => g_sim,
g_stamp_date => g_stamp_date,
g_stamp_time => g_stamp_time,
g_stamp_svn => g_stamp_svn,
g_design_name => c_design_name,
g_design_note => c_design_note,
g_fw_version => c_fw_version,
g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
g_dp_clk_use_pll => FALSE,
g_app_led_red => c_app_led_en,
g_app_led_green => c_app_led_en,
g_use_phy => c_use_phy,
g_aux => c_aux
)
PORT MAP (
--
-- >>> SOPC system with conduit peripheral MM bus
--
-- System
cs_sim => cs_sim,
xo_clk => xo_clk,
xo_rst_n => xo_rst_n,
mm_clk => mm_clk,
mm_locked => mm_locked,
mm_rst => mm_rst,
dp_rst => OPEN,
dp_clk => OPEN,
dp_pps => dp_pps,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
this_chip_id => this_chip_id,
this_bck_id => OPEN,
app_led_red => app_led_red,
app_led_green => app_led_green,
-- PIOs
pout_debug_wave => pout_debug_wave,
pout_wdi => pout_wdi,
-- Manual WDI override
reg_wdi_mosi => reg_wdi_mosi,
reg_wdi_miso => reg_wdi_miso,
-- . PPSH
reg_ppsh_mosi => reg_ppsh_mosi,
reg_ppsh_miso => reg_ppsh_miso,
-- system_info
reg_unb_system_info_mosi => reg_unb_system_info_mosi,
reg_unb_system_info_miso => reg_unb_system_info_miso,
rom_unb_system_info_mosi => rom_unb_system_info_mosi,
rom_unb_system_info_miso => rom_unb_system_info_miso,
-- UniBoard I2C sensors
reg_unb_sens_mosi => reg_unb_sens_mosi,
reg_unb_sens_miso => reg_unb_sens_miso,
-- eth1g
eth1g_tse_clk => eth1g_tse_clk,
eth1g_mm_rst => eth1g_mm_rst,
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
eth1g_reg_mosi => eth1g_reg_mosi,
eth1g_reg_miso => eth1g_reg_miso,
eth1g_reg_interrupt => eth1g_reg_interrupt,
eth1g_ram_mosi => eth1g_ram_mosi,
eth1g_ram_miso => eth1g_ram_miso,
--
-- >>> Ctrl FPGA pins
--
-- General
CLK => CLK,
PPS => PPS,
WDI => WDI,
INTA => INTA,
INTB => INTB,
-- Others
VERSION => VERSION,
ID => ID,
TESTIO => TESTIO,
-- I2C Interface to Sensors
sens_sc => sens_sc,
sens_sd => sens_sd,
ETH_clk => ETH_clk,
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT
);
u_mmm : ENTITY work.mmm_unb1_ddr3
GENERIC MAP(
g_sim => g_sim,
g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr
)
PORT MAP (
-- GENERAL
xo_clk => xo_clk,
xo_rst_n => xo_rst_n,
xo_rst => xo_rst,
mm_rst => mm_rst,
mm_clk => mm_clk,
mm_locked => mm_locked,
cal_clk => cal_clk,
pout_wdi => pout_wdi,
-- Manual WDI override
reg_wdi_mosi => reg_wdi_mosi,
reg_wdi_miso => reg_wdi_miso,
-- . PPSH
reg_ppsh_mosi => reg_ppsh_mosi,
reg_ppsh_miso => reg_ppsh_miso,
-- system_info
reg_unb_system_info_mosi => reg_unb_system_info_mosi,
reg_unb_system_info_miso => reg_unb_system_info_miso,
rom_unb_system_info_mosi => rom_unb_system_info_mosi,
rom_unb_system_info_miso => rom_unb_system_info_miso,
-- UniBoard I2C sensors
reg_unb_sens_mosi => reg_unb_sens_mosi,
reg_unb_sens_miso => reg_unb_sens_miso,
-- DDR3
reg_io_ddr_mosi => reg_io_ddr_mosi,
reg_io_ddr_miso => reg_io_ddr_miso,
-- Diagnostics
reg_diagnostics_mosi => reg_diagnostics_mosi,
reg_diagnostics_miso => reg_diagnostics_miso,
-- eth1g
eth1g_tse_clk => eth1g_tse_clk,
eth1g_mm_rst => eth1g_mm_rst,
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
eth1g_reg_mosi => eth1g_reg_mosi,
eth1g_reg_miso => eth1g_reg_miso,
eth1g_reg_interrupt => eth1g_reg_interrupt,
eth1g_ram_mosi => eth1g_ram_mosi,
eth1g_ram_miso => eth1g_ram_miso
);
u_areset_ddr_ref_rst : ENTITY common_lib.common_areset
GENERIC MAP(
g_rst_level => '1',
g_delay_len => 40
)
PORT MAP(
clk => CLK,
in_rst => mm_rst,
out_rst => ddr_ref_rst
);
u_node : ENTITY work.node_unb1_ddr3
GENERIC MAP (
g_sim => g_sim,
g_technology => c_technology,
g_tech_ddr => c_tech_ddr,
g_st_dat_w => g_st_dat_w
)
PORT MAP (
-- System
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
ddr_ref_clk => CLK,
ddr_ref_rst => ddr_ref_rst,
-- Clock outputs ddr_out_clk => dp_clk,
ddr_out_rst => dp_rst,
-- MM interface
reg_io_ddr_mosi => reg_io_ddr_mosi,
reg_io_ddr_miso => reg_io_ddr_miso,
reg_diagnostics_mosi => reg_diagnostics_mosi,
reg_diagnostics_miso => reg_diagnostics_miso,
MB_I_IN => MB_I_IN,
MB_I_IO => MB_I_IO,
MB_I_OU => MB_I_OU
);
END str;