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Commit f4284e9c authored by Pieter Donker's avatar Pieter Donker
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L2SDP-307, removed C_N_sub_bf

parent 2b452acc
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1 merge request!29L2SDP-307, working version.
...@@ -47,7 +47,6 @@ ...@@ -47,7 +47,6 @@
#define C_Q_fft 2 #define C_Q_fft 2
#define C_N_sub 512 #define C_N_sub 512
#define C_N_pol_bf 2 #define C_N_pol_bf 2
#define C_N_sub_bf 488
#define C_S_sub_bf 488 #define C_S_sub_bf 488
#define C_N_step 1 #define C_N_step 1
#define C_N_crosslets_max 7 #define C_N_crosslets_max 7
......
...@@ -156,8 +156,8 @@ Fpga::Fpga(list<class Node*>& nodelist, const int32_t n_beamsets): ...@@ -156,8 +156,8 @@ Fpga::Fpga(list<class Node*>& nodelist, const int32_t n_beamsets):
pointMap->add_register("FPGA_scrap_R", "fpga/scrap", nodes.size(), C_N_scrap, "RO", REG_FORMAT_UINT32); pointMap->add_register("FPGA_scrap_R", "fpga/scrap", nodes.size(), C_N_scrap, "RO", REG_FORMAT_UINT32);
pointMap->add_register("FPGA_scrap_RW", "fpga/scrap", nodes.size(), C_N_scrap, "RW", REG_FORMAT_UINT32); pointMap->add_register("FPGA_scrap_RW", "fpga/scrap", nodes.size(), C_N_scrap, "RW", REG_FORMAT_UINT32);
pointMap->add_register("FPGA_weights_R", "fpga/weights", nodes.size(), C_S_pn*nBeamsets*C_N_sub_bf, "RO", REG_FORMAT_INT16); pointMap->add_register("FPGA_weights_R", "fpga/weights", nodes.size(), C_S_pn*nBeamsets*C_S_sub_bf, "RO", REG_FORMAT_INT16);
pointMap->add_register("FPGA_weights_RW", "fpga/weights", nodes.size(), C_S_pn*nBeamsets*C_N_sub_bf, "RW", REG_FORMAT_INT16); pointMap->add_register("FPGA_weights_RW", "fpga/weights", nodes.size(), C_S_pn*nBeamsets*C_S_sub_bf, "RW", REG_FORMAT_INT16);
pointMap->add_register("FPGA_signal_input_data_buffer_R", "fpga/signal_input_data_buffer", nodes.size(), C_S_pn*C_V_si_db, "RO", REG_FORMAT_INT16); pointMap->add_register("FPGA_signal_input_data_buffer_R", "fpga/signal_input_data_buffer", nodes.size(), C_S_pn*C_V_si_db, "RO", REG_FORMAT_INT16);
pointMap->add_register("FPGA_signal_input_histogram_R", "fpga/signal_input_histogram", nodes.size(), C_S_pn*C_V_si_histogram, "RO", REG_FORMAT_UINT32); pointMap->add_register("FPGA_signal_input_histogram_R", "fpga/signal_input_histogram", nodes.size(), C_S_pn*C_V_si_histogram, "RO", REG_FORMAT_UINT32);
......
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