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Commit c11d0427 authored by Gijs Schoonderbeek's avatar Gijs Schoonderbeek
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Ping FPGA, 10Mbit to pi only what's needed

parent 6ce09ca7
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1 merge request!2Modified the scripts to run on Raspberry Pi.
......@@ -31,6 +31,15 @@ device = 0
# Enable SPI
spi = spidev.SpiDev()
# Open a connection to a specific bus and device (chip select pin)
spi.open(bus, device)
# Set SPI speed and mode
spi.max_speed_hz = 1000000
#spi.max_speed_hz = 50000
spi.mode = 1
cmd_normal_read = 0x60
cmd_normal_write = 0x61
......@@ -75,12 +84,12 @@ def read_switch(page, addr, pr_stri = True):
print("read error")
return ret
def write_switch_bytes(page, addr, data):
def write_switch_bytes(page, addr, data, pr_stri = True):
stri = '> write switch from page: 0x{0:0>2x}, address: 0x{1:0>2x} data 0x'.format(page, addr)
for byte_cnt in range(len(data)):
# add_stri = "{0:0>2x}".format(data[len(data)-1-byte_cnt])
add_stri = "{0:0>2x}".format(data[-1-byte_cnt])
stri += add_stri
if pr_stri:
print(stri)
read_register(0xfe)
ret = spi.xfer2([cmd_normal_write, 0xff, page])
......@@ -112,6 +121,8 @@ def read_link_status(ports=16):
ret = read_switch(0x01,0x20+cnt, pr_stri = False)
if ret[1] & 0x01:
stri += "link up "
else:
stri += "link down "
if ret[1] & 0x02:
stri += "dupplex "
else:
......@@ -132,9 +143,7 @@ def read_link_status(ports=16):
if ret[2] & 0x04:
stri += "Rx: Er "
if ret[2] & 0x40:
stri += "Rx FIFO: Er "
else:
stri += "link down "
stri += "Rx FIFO Er "
print(stri)
# Read phy registister status
for cnt in range(4):
......@@ -148,11 +157,15 @@ def read_link_status(ports=16):
stri += "remote fault "
# print(stri)
ret = read_switch(0x80+cnt,0x14, pr_stri = False)
stri += " 1000BASE-T status ch{} ".format(cnt)
stri += " link status ch{} ".format(cnt)
if ret[2] & 0x10:
stri += "remote status is good "
else:
stri += "remote status is NOK "
if ret[2] & 0x20:
stri += "local status is good "
else:
stri += "local status is NOK "
if ret[2] & 0x40:
stri += "local master"
else:
......@@ -160,7 +173,8 @@ def read_link_status(ports=16):
else:
stri += " No link "
print(stri)
write_switch_bytes(0x80+cnt, 0x3c, [0x35, 0x08])
if 0:
write_switch_bytes(0x80+cnt, 0x3c, [0x35, 0x08], pr_stri = False)
ret = read_switch(0x80+cnt,0x3e)
if 0:
print("Drop packet count register")
......@@ -173,25 +187,16 @@ def read_link_status(ports=16):
read_switch(0x0,0x60 + cnt)
read_switch(0x0,0x10)
read_switch(0x0,0x20)
if 1:
print("Receive count register")
if 1:
print("Receive count register")
for cnt in range(16):
write_switch_bytes(0x10+cnt, 0x20, [0xD0, 0x09])
# Set to receive packet count
write_switch_bytes(0x10+cnt, 0x20, [0xD0, 0x09], pr_stri = False)
time.sleep(0.5)
for cnt in range(16):
# read_switch(0x41,0x80+2*cnt)
read_switch(0x10+cnt,0x2e)
# Open a connection to a specific bus and device (chip select pin)
spi.open(bus, device)
# Set SPI speed and mode
spi.max_speed_hz = 1000000
#spi.max_speed_hz = 50000
spi.mode = 1
if len(sys.argv) < 2:
......@@ -208,57 +213,33 @@ if len(sys.argv) < 2:
elif sys.argv[1] == "stat":
read_link_status(16)
elif sys.argv[1] == "set":
#b print("write and read led register")
#b write_switch_bytes(0x00, 0x24, [0x20, 0x02]) #LSB first
#b read_switch(0x00,0x24)
#nth print("write and read jumbo register")
#nth write_switch_bytes(0x40, 0x01, [0xff, 0xff, 0x00, 0x00])
#nth read_switch(0x40,0x01)
#b print("strap resistors")
#b read_switch(0x01,0x70)
# Extra setting for the switch, not needed, bonus settings
if 0:
print("write and read led register")
write_switch_bytes(0x00, 0x24, [0x20, 0x02]) #LSB first
read_switch(0x00,0x24)
print("write and read jumbo register")
write_switch_bytes(0x40, 0x01, [0xff, 0xff, 0x00, 0x00])
read_switch(0x40,0x01)
print("strap resistors")
read_switch(0x01,0x70)
# required setting for the switch
if 1:
# for ch_cnt in range(16):
# print("write and read SGMII register CH0, fifo size max")
# write_switch_bytes(0x10, 0x24, [0x44, 0x00])
# read_switch(0x10,0x24)
# print("write and read SGMII register CH3, fifo size max")
# write_switch_bytes(0x13, 0x24, [0x44, 0x00])
# read_switch(0x13,0x24)
# write_switch_bytes(0x0, 0x20, [0x06]) #Switch mode)
# for cnt in range(16):
# write_switch_bytes(0x0, 0x0+cnt, [0x00]) #Overwrite strapping resistor unmanaged mode
# write_switch_bytes(0x10+ch_cnt, 0x24, [0x44, 0x00])
# read_switch(0x10+ch_cnt,0x24)
speed_100Mbit = False
speed_1000Mbit = False
for ch_cnt in range(4):
print("Set PHY ch 0 and read back to 10 Mbit 0x01 100Mbit 0x21")
write_switch_bytes(0x80+0, 0x00, [0x00, 0x01])
#b ret = read_switch(0x80,0x00)
print("Set PHY ch 1 and read back to 10 Mbit 0x01 100Mbit 0x21")
write_switch_bytes(0x00, 0x60+1, [0x8B])
write_switch_bytes(0x10+1, 0x00, [0x40, 0x11])
write_switch_bytes(0x80+1, 0x00, [0x40, 0x01])
#1 write_switch_bytes(0x10+1, 0x00, [0x00, 0x01])
#1 print("Set PHY ch 3 and read back to 10 Mbit 0x01 100Mbit 0x21")
#1 write_switch_bytes(0x80+3, 0x00, [0x00, 0x01])
#b ret = read_switch(0x80+3,0x00)
#1 write_switch_bytes(0x00, 0x86, [0xa0]) # no polling (make no difference)
for cnt in [15, 14, 13, 12, 11, 10, 9, 8]: #, 7, 6, 5, 4]:
write_switch_bytes(0x00, 0x60+cnt, [0x8B])
write_switch_bytes(0x80 + ch_cnt, 0x00, [(0x00 | (speed_1000Mbit << 6)), (0x01 | (speed_100Mbit << 5))])
write_switch_bytes(0x00, 0x60 + ch_cnt, [(0x83 | (speed_100Mbit << 2) | (speed_1000Mbit << 3))]) # fix PHY ports to 10 Mbit
# Set the FPGA links to disable Auto negatiation
for cnt in [15, 13, 11, 9]: # only ETH0 interface
write_switch_bytes(0x00, 0x60+cnt, [0x8B]) #Fix FPGA links
else:
print("spi_switch_Unb2c stat for status")
print("spi_switch_Unb2c set to set registers")
# Not working as espected
#print("switch off ch 0")
#write_switch_bytes(0x10, 0x00, [0x18, 0x40, 0x18, 0x40])
#read_switch(0x10,0x00)
if 0:
print("Tx pause status ")
read_switch(0x01,0x14)
print("Rx pause status ")
read_switch(0x01,0x18)
write_switch_bytes(0x30, 0x00, [0x40])
read_switch(0x30,0x00)
write_switch_bytes(0x00, 0x20, [0x11])
read_switch(0x00,0x20)
spi.close()
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