dp_complex_mult.vhd

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--
-- Copyright (C) 2017
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
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--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
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LIBRARY IEEE, common_lib, dp_lib, common_mult_lib, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE common_lib.common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;

-- Author:
-- . Daniel van der Schuur
-- Purpose:
-- . Provide an array of complex multipliers with streaming array I/O types
-- Description:
-- . Multiplies snk_in_2arr_2[i][0] with snk_in_2arr_2[i][1] yielding 
--   src_out_2arr[i] for i in 0..g_nof_multipliers-1.
-- . This DP wrapper does not allow selection of RTL implementation of 
--   common_complex_mult; it uses the generated IP core for g_technology.

ENTITY dp_complex_mult IS
  GENERIC (
    g_technology      : NATURAL := c_tech_select_default;
    g_nof_multipliers : NATURAL;
    g_conjugate_b     : BOOLEAN := FALSE; -- Conjugate input 1 of snk_in_2arr2(i)(1 DOWNTO 0)
    g_data_w          : NATURAL -- Input data width. Output data width = 2*input data width.
   ); 
  PORT (
    rst            : IN  STD_LOGIC;
    clk            : IN  STD_LOGIC;

    snk_in_2arr_2  : IN  t_dp_sosi_2arr_2(g_nof_multipliers-1 DOWNTO 0);

    src_out_arr   : OUT t_dp_sosi_arr(g_nof_multipliers-1 DOWNTO 0)
  );
END dp_complex_mult;

ARCHITECTURE str OF dp_complex_mult IS

  CONSTANT c_pipeline : NATURAL := 3; -- Delay introduces by IP multiplier used
 
  SIGNAL common_complex_mult_src_out_arr : t_dp_sosi_arr(g_nof_multipliers-1 DOWNTO 0);
  SIGNAL dp_pipeline_src_out_arr         : t_dp_sosi_arr(g_nof_multipliers-1 DOWNTO 0);

BEGIN

  -----------------------------------------------------------------------------
  -- Complex Multipliers
  -----------------------------------------------------------------------------
  gen_common_complex_mult : FOR i IN 0 TO g_nof_multipliers-1 GENERATE
    u_common_complex_mult : ENTITY common_mult_lib.common_complex_mult
    GENERIC MAP (
      g_technology       => g_technology,
      g_variant          => "IP",
      g_in_a_w           => g_data_w,
      g_in_b_w           => g_data_w,
      g_out_p_w          => 2*g_data_w,     -- default use g_out_p_w = g_in_a_w+g_in_b_w
      g_conjugate_b      => g_conjugate_b
    )
    PORT MAP (
      clk        => clk,
      clken      => '1',
      rst        => '0',
      in_ar      => snk_in_2arr_2(i)(0).re(g_data_w-1 DOWNTO 0),
      in_ai      => snk_in_2arr_2(i)(0).im(g_data_w-1 DOWNTO 0),
      in_br      => snk_in_2arr_2(i)(1).re(g_data_w-1 DOWNTO 0),
      in_bi      => snk_in_2arr_2(i)(1).im(g_data_w-1 DOWNTO 0),
      in_val     => snk_in_2arr_2(i)(0).valid,
      out_pr     => common_complex_mult_src_out_arr(i).re(2*g_data_w-1 DOWNTO 0),
      out_pi     => common_complex_mult_src_out_arr(i).im(2*g_data_w-1 DOWNTO 0),
      out_val    => common_complex_mult_src_out_arr(i).valid
    );     

    src_out_arr(i).re    <= RESIZE_DP_DSP_DATA(common_complex_mult_src_out_arr(i).re(2*g_data_w-1 DOWNTO 0));
    src_out_arr(i).im    <= RESIZE_DP_DSP_DATA(common_complex_mult_src_out_arr(i).im(2*g_data_w-1 DOWNTO 0));
    src_out_arr(i).valid <= common_complex_mult_src_out_arr(i).valid;  
  END GENERATE;

  -----------------------------------------------------------------------------
  -- Forward the input sync with the correct latency
  -----------------------------------------------------------------------------
  u_common_pipeline_sl : ENTITY common_lib.common_pipeline_sl
   GENERIC MAP (
     g_pipeline  => c_pipeline
   )
   PORT MAP (
     rst     => rst,
     clk     => clk,
 
     in_dat  => snk_in_2arr_2(0)(0).sync,
     out_dat => src_out_arr(0).sync
   );
 
END str;