hdllib.cfg

hdl_lib_name = unb1_ddr3
hdl_library_clause_name = unb1_ddr3_lib
hdl_lib_uses_synth = common technology mm i2c unb1_board dp eth diagnostics io_ddr tech_ddr
hdl_lib_uses_sim = 
hdl_lib_technology = ip_stratixiv
hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master

synth_files =
    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.vhd
    src/vhdl/node_unb1_ddr3.vhd
    src/vhdl/mmm_unb1_ddr3.vhd
    src/vhdl/unb1_ddr3.vhd
    
test_bench_files = 
    tb/vhdl/tb_unb1_ddr3.vhd

[modelsim_project_file]

modelsim_copy_files = 
   $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl

modelsim_compile_ip_files =
    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
    

[quartus_project_file]
synth_top_level_entity =

quartus_copy_files =
    quartus/sopc_unb1_ddr3.sopc .
    $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl

quartus_qsf_files =
    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
    
quartus_qip_files =
    $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.qip

quartus_tcl_files =
    quartus/unb1_ddr3_pins.tcl
    quartus/unb1_ddr3_pins_constraints.tcl
    
quartus_sdc_files =
    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
    

nios2_app_userflags = -DCOMPILE_FOR_SOPC