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  • HPR-158
  • L2SDP-1082
  • L2SDP-LIFT
  • master default protected
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Created with Raphaël 2.2.016Apr15141312109873231Mar30272625242320191817161312111096543227Feb2625242320191817-Hooked up the MM control reg bus of the block gens;-Set g_use_bg to TRUE;Fixed default value of wr_snk_out.xon to '1'. This fixes the DDR3 issue on hardware.-Added development remarks in comment block.-Set override default of channel field to 0 (data path).-Replaced mixed width FIFO (64b->32b) with dp_fifo_sc + dp_rapack_data soadded fifo in between bg and dp_offloadadaption for new tx/rx_offload-Added TCPDUMP PCAP file and resulting plots saved in PNG pic.-Fixed tyope in comment.-Fixed extraction of complex values from PCAP file;UPDated script to new DDR3 -Fixed off-by-one-byte.-Cleaned the code.-Added plotting!-Added visibility extraction.Initial commit Initial commit COpy-Added header field extraction.-Added new Python test case.-Added ASTRON_SP_059_APERTIF_Correlator_output_data_format_specification;Renameinverted mm_rst for QSYS input reset_ninverted mm_rst for QSYS reset_n input1 more streamAdded more signals to registerRemoved unused constants-Added diag data buffers to top level (input stage);updated pinning constraintsIn sim run on bn 3 instead of fn 0.Removed unused g-sim from reorder_lib.reorder_transpose.-Removed g_no_dsp from correlator module;Use DDR3 phy records t_tech_ddr3_phy_in from tech_ddr_pkg.Use default reg_io_ddr_mosi input value to allow not connecting it.Removed unused g_sim.-Fixed reordering (it was mirrorred).Use phy records from tech_ddr_lib.tech_ddr_pkg. Use tech_ddr_lib.tech_ddr_memory_model.Use c_blocks_per_sync = 16 in simulation.Use record field RESIZE_*() functions.