Skip to content
Snippets Groups Projects

Repository graph

You can move around the graph by using the arrow keys.
Select Git revision
  • HPR-158
  • L2SDP-1073
  • L2SDP-1074
  • L2SDP-1113
  • L2SDP-LIFT
  • master default protected
6 results
Created with Raphaël 2.2.024Feb23222117161514139876432126Jan252419181712114223Dec2221201916158752130Nov2928252422211817161413987432131Oct282726252421201918171413121110764329Sep282221201915141331Aug30292625242322171615121110954-Fixed a typo in a comment.-Finished skeleton (everything compiles OK in ModelSim).-Added type.-Deleted log files.-Added arts_unb1_sc4.-Added pps_delay register.-Added common_pulse_delay skeleton file.Updated text.Added command line parser and __main__. Added class description docstringsAdded commented system info MM slaves.-Added extra 200MHz pll output clock.Changed config file extension from .cfg into .yamlChanged c_ into g_. Import common.py as cm. This also means that in the peripheral YAML files cm.c_nof_complex and cm.celi_log2() habe to be used.Remove unnecesary indent after ---Import common.py as cm. This also means that in the peripheral YAML files cm.c_nof_complex and cm.celi_log2() habe to be used.Changed c_ into g_. Use g_weights_w = 8 to see that it overrules the default 16.-Changed band/uniboard range from 0:13,15 to 1:15.Merged common.py to make them the same in /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk and /home/kooistra/svnroot/UniBoard_FP7/RadioHDL/trunk.Added peripheral.cfg.Removed unnecessary indent after ---Removed unnecessary indent after ---Commented peri_lib, probably because display_system() in peripheral.py already prints info.Added print ram.widthReplace diag_block_gen by mms_diag_block_gen.Replace diag_data_buffer by mms_diag_data_buffer.Added tb_mms_dp_bsn_source.vhd.Changed capture current BSN into capture BSN at sync.Added g_sim_level => 0.Commented tb_node_apertif_unb1_correlator_input.vhdCorrected sensitivity list of process p_extract_bf_streams_for_db. No need to account for +1 bit growth in c_fs_quant_in_dat_w, because phasor has amplitude 1No change, comment only.no need for + c_sum_of_prod_w in c_product_w, because phasor amplitude is 1Added parameter c_weigths_wAdded more peripherals. Added peripheral label to support muliple occurances in one design.Back to r15465 but keep #src/vhdl/apertif_cor_mesh_distr.vhd in comment.Support Added src/vhdl/apertif_cor_mesh_distr.vhd to apertif_lib.No change, added alternative commented #REC_FILE lines.No change, added commented print i.