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  • HPR-158
  • L2SDP-1082
  • L2SDP-LIFT
  • master default protected
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Created with Raphaël 2.2.023Sep22212017161510987632131Aug2625242320191811109654331Jul30232221201915141397652129Jun25242322211817151411109432131May2827262520191712107654329Apr28232220191514131298762131Mar30292524231918171615121110985432126Feb252423221512109432129Jan2826Log name in proc_dp_verify_value().Merge branch 'L2SDP-497' into 'master'Merge branch 'L2SDP-476' into 'master'Fixed regression testsAdded first version of dp_bsn_align_v2.vhd with mmp and tb. This was accidentially on L2SDP-495 branch, but should be on this L2SDP-290 branch.Merge branch 'master' into L2SDP-497Merge branch 'master' into L2SDP-490Merge branch 'L2SDP-494' into 'master'Merge branch 'L2SDP-495' into 'master'Corrected wront --> wrong.JESD outputs data on upper 14 bits instead of lower 14 bitsRemove accidental commit of dp_stream_pkg.vhf for dp_bsn_align_v2 in this L2SDP-495 branch.Remove accidental commit of dp_bsn_align_v2 in this L2SDP-495 branch.added 27b complex mult for e2sgImproved comments. Use r.enable instead of v.enable to ease timing closure. This required using expected_out_enable2 in tb for g_block_size = 2.added 27 bit complex mult to hdllibMerge branch 'master' into L2SDP-494Added check on sdp_integration_interval field in header.Added complex multiplier 27 bits IPCorrected integration_interval field value is index + 1.Added RAM_ST_HISTOGRAM. Corrected mm_port_span of RAM_ST_XSQ. Corrected missing mon_output_sync_bsn field in REG_BSN_SYNC_SCHEDULER_XSUB.Added missing mon_input_bsn_at_sync field and corrected address_offsets.Corrected mm_port_span for RAM_ST_XSQ.Merge branch 'master' into L2SDP-290Merge branch 'L2SDP-482' into 'master'Merge branch 'L2SDP-425' into 'master'processed review commentsprocessed review commentsNo need yet to support 27b mult for unb1.updated mmap.gold/ mmap.qsys.goldRemoved obsolete g_sim from common_complex_mult instances.Cleanup the tb.Prepared for 27b IP. Removed not used g_sim. Cleaned up generate statements, tb stimuli and descriptions.Removed not used and confusing g_sim (was intended for test data using & instead of *).Added tb_tb_common_complex_mult.vhd to regression test, to test IP and RTL en 18b and 27b variants.set reset value of interval counter to 1 instead of 0 as it is a totaladded missing st_lib librarycorrected user_widthadded st_histogram to yaml filesadded st_histogram ip file