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  • HPR-158
  • L2SDP-1082
  • L2SDP-LIFT
  • master default protected
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Created with Raphaël 2.2.011Sep109874329Aug272524212019181714131211105431Jul3028232221201615141310987632130Jun292625242322191817161512111098543231May29282726222120151413121187641update different bus widths for testing6xQSFP, 24xBCK10GbE testing update10GbE settingsfor mm_clk default using fplltesting different channel configs-Commented out pipeline stage between mesh and BF as it caused errors.-Disconnected MM control bus to relax timing.-Added unb1_board.sdc.-Added DDR3 controller-generated clock (4G single rank).deleted because correct name is ip_arria10_pll_xgmii_mac_clocks.qsys-Cleaned code.-Fixed comment.-Fixed comment.-Added generated HEX file for 16b subband selection (out=in, no reordering).-Added Second ss_parallel stage (+ FIFOs and 16b->8b->16b rewiring) to top -Renamed Python file to generate HEX files.-Changed names/paths of generated HEX files in preperation for the second set-SVN copied gen_hex_files_ss_parallel.py.-Added SDC file include!-Set base IP range to 10.195.xx.yy.Create unb1_rfidb initial design (sim and synth tested OK)Correct library name (uorl => detector_lib)-Ported tb_aartfaac_sdo.vhd to RadioHDL. Sim compiles and runs OK.-Copied dp_stream_player.vhd to RadioHDL.-Set g_sim_flash_model to FALSE by default as it causes sim issues in multi-SVN copied tb_aartfaac_sdo to RadioHDL.-Ported aartfaac_fn_sdo to RadioHDL:-Modified source to be RadioHDL compatible;-Fixed path.-Added dir struct and copied files over from $AARTFAAC to $RADIOHDL.-Restored g_blk_sync in mms_diag_block_gen.vhd as it is required for -Added TCL pin file.-Replaced avs_eth_0 instance with the RadioHDL-compatible one.-Removed references to non-existent DDR3 generic.-Added missing VHDL file (node_fn_bf) to hdllib.cfg.cosmetics Added pipeline add output of transpose Added pipline between input fifo and dp_offload