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Created with Raphaël 2.2.022Feb2120141312876131Jan2518171110521Dec201918730Nov2423222120151413128762131Oct26252423222019171611109543228Sep272625212019181413126531Aug3029282524222118171615141098731Jul27262565427Jun2115141312752125May242317151110982126Apr25201817117654331Mar3028272322212017161514107227Feb2423Use nof_bdo_destinations_max = 16 as a better compromis.Use c_sdp_bdo_reorder_nof_blocks_max = 16 as a better compromis.Clarified how sync is poassed on through the FIFO.Merge branch 'master' into L2SDP-1011initial commit of cocotb tb_rdma_packetiserPut input delay buffer after WG.Add comment on FIFO data width.Decrease buffer to 1024 to save M20K RAM.Adjust sim_done to fix tb result.Merge branch 'L2SDP-1007' into 'master'Remove note on Quartus segmentation error. Explain c_sdp_bdo_reorder_nof_blocks_max = 4 and nof_bdo_destinations_max = 8.Correct i_dp_sosi_arr().data in p_deframer process.Use g_use_ctrl = false in rx_clk --> dp_clk FIFO.Explicitly set dplink_siso_arr(i).xon. Remove duplicate assignment of dp_sosi_arr and dp_sosi.Apply dp_ready FIFO flow control in generate loop, instead of using func_dp_stream_arr_set(dplink_siso_arr, dp_ready, 'READY')Use c_sdp_bdo_reorder_nof_blocks_max = 4 to save block RAM. Ensure c_sdp_bdo_reorder_nof_blocks_max <= nof_bdo_destinations_max in revision. Choose nof_bdo_destinations_max = 8.Default assign dplink_siso_arr to avoid synthesis warning on latch on xon.Use nof_bdo_destinations_max = 8 instead of 32, to save block RAM.Add g_no_st_histogram = true default, to save block RAM.Use g_use_tech_jesd204b_v2 as generic instead of internal constant, to allow different selection in designs.Manually add sosi arr if necessary.Add missing wire out_sosi_arr <= st_sosi_arr.Use wr_rst based on core_pll_locked for FIFO.Correct jesd_ctrl_mosi interface connection.Use sdp_adc_input_and_timing.vhd. Support tech_jesd204b and tech_jesd204b_v2.Add output dp_sysref to v2.tb_tech_jesd204_v2.vhd was used.Merge branch 'master' into L2SDP-1007Verified with tb_tech_jes204b.vhd.Make equivalent to ip_arria10_e2sg_jesd204b_v2.vhdMake equivalent to ip_arria10_e2sg_jesd204b.vhdAdd v2Add debug signals. Correct single cycle rxlink_sysref. Correct FIFO data width to c_jesd204b_rx_framer_data_w.Add debug signals. Improve layout of p_deframer.Correct indent.Add v2 components.Add ip_arria10_e2sg_jesd204b_v2.vhd with clock domain crossing FIFO in IPAdd default for input in_aux.Renamed some signals to make them more clear.Small comment cleans.