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  • HPR-158
  • L2SDP-1073
  • L2SDP-1074
  • L2SDP-1113
  • L2SDP-LIFT
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Created with Raphaël 2.2.026May22212015141312118764130Apr29282423222120171615141312109873231Mar302726252423201918171613121110965Added g_use_clkbuf=TRUE to use ALTCLKCTRL. Added g_use_fpll=FALSE to use IOPLL, but the option is to use a fractional PLL.Added global clock buffer IPAdded fractional PLL IP with similar c0, c1 and c2 as the pll_clk200 IO PLL.Added fractional PLL IP with similar c0, c1 and c2 as the pll_clk200 IO PLL.Added global clock buffer IPthis (temporary) debug version has epcs,remu,plls removed and tse,mm_clkusing 125MHz clock for mm_clknew -t option documented for python scriptsCommented QSFP_* INOUT ports because they are not connected and thus cause a fitter warning.Debug: for single board application force bck_id = 0 to avoid need to set the bck_id input.-Undid use of environment var.-Using envoronment var to point to VHD file.Added commented debug statements to drive the clocks without the PLL.Renamed elk25 into mm_sim_clk, removed unnecessary i_ prefixes. Removed obsolute dp_dis.Removed cal_clk because it is not needed on arria10 of uniboard2.CHanged default to stratixivMove the unb2_board_clk_rst.vhd functionality to unb2_board_node_ctrl.vhd. Rename sys_clk into mm_clk.Added two function: remove_all_but_the_dict_from_list and get_key_value Added rm generated to remove the existing generated files before regenerating them.Updated all IP related files to match Quartus 15.0 which uses libraries with _150 in their names instead of -141.For now use /tools/quartus/check_ipx_content only for quartus 15.0, because the dir path for 11.1sp2 is 11.1 and thus does not fit.Define toolset unb2 to use Quartus v15.0. Upgrade all Arria10 IP. Use check_ipx_content in set_quartus. Created /15.0 with the simulation models.Define toolset unb2 to use Quartus v15.0.Upgraded Arria10 Qsys IP components to Quartus 15.0 and set device family to 10AX115U4F45I3SGES for UniBoard2 v0Upgrade to Quartus 15.0 and set device family 10AX115U4F45I3SGES for UniBoard v0.UniBoard2 v0 has FPGA device family 10AX115U4F45I3SGES and fitter requires MIN_CORE_JUNCTION_TEMP 0.changed device name into device family to match Quartus.Photo of the first UniBoard2 with the exact Arria10 device name.-Added even more comments.-Added comment-Disabling data path up front to fix weird plotting issue.-Added subband stat readout and plotting.-Added script to verify 24 SP from rack BN -> FN -> XC.-Added TC to read the 12 input data buffers.-Fixed a typo.Added nof_blocks to 800000-Removed comments so Python peripheral to extract regmap.dded 10/8 margin to BSN monitor sync timeout.v0.1, 2015-05-13, E. Kooistra, First draft that describes the CB input.-Added peripheral to control visibility packet header fields.