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Created with Raphaël 2.2.017Jan1110521Dec201918730Nov2423222120151413128762131Oct26252423222019171611109543228Sep272625212019181413126531Aug3029282524222118171615141098731Jul27262565427Jun2115141312752125May242317151110982126Apr25201817117654331Mar3028272322212017161514107227Feb24232221171615987RTSD-181: Clearified issue and use for Agilex7 in information header.RTSD-181: Added severity error for Agilex7, when two different clocks are used.Merge branch 'RTSD-242' into 'master'Merge branch 'master' into RTSD-242Update iir_filter.ipynb and rerun other ipynb.Add Planning topics Transient detection.Add iir_biquad_butter_coefficients(), for biquads used in TBB.More on IIR.Add paper.Merge branch 'RTSD-230' into 'master'Merge branch 'master' into RTSD-230RTSD-230: Changed filename and included content.Merge branch 'RTSD-247' into 'master'All pass IIR filter desing by F. Harris.RTSD-247: Fix typo.RTSD-247: Address feedback from merge request. Address unclear line number 103.Merge branch 'master' into RTSD-230Merge branch 'master' into RTSD-247RTSD-247: Created new Reset Release IPs version 1e1v for iwave using Agilex7 AGIB027R31B1E1V, that is necessary to use in all Stratix10 and Intel Agilex devices, for us in the iwave BSP (Boards). That was the result of a critical warning during synthesis.Merge branch 'RTSD-229' into 'master'Updated DEVICE AGIB027R31A1I1VB -> AGIB027R31B1E1VRTSD-230: The directory name has been shortened in consideration of the future library name, and the project name (application) has been changed to <part>_<buildset> to prevent confusion with a board design.Try scipy.signal. iirdesign().Add scipy.signal.iirdesign()Add log option to plot_iir_filter_analysis()IIR analysis.Support no plot in zplane().Support show argument in plot_iir_filter_analysis().Added IIR section.Merge branch 'RTSD-229' into 'master'Merge branch 'master' into RTSD-209RTSD-209: See README for reason distinction (lofar2 vs alma). Intended to be top-level entity for synthesis with alma par to investigate resource usage, timing paths and max clockfreq for iwave Agilex 7. Currently the same as lofar2. Added with multiple comment with which par have to be changed.RTSD-209: See README for reason distinction (lofar2 vs alma). Added synthesis project for wpfb_unit_dev.vhd to investigate resource usage, timing paths and max clockfreq for iwave Agilex 7 with lofar2 par.RTSD-209: Added synthesis project for wpfb_unit_dev.vhd to investigate resource usage, timing paths and max clockfreq for iwave Agilex 7.Write about synthesis (folder), critical warnings and it is fully adapted for the Agilex 7. Most important results are refered.Add plot_iir_filter_analysis() based on LTF-IIR-allgemein.ipynbcode from https://github.com/chipmuenk .Original file from https://github.com/chipmuenk.set new path for vhdl_styleMerge branch 'master' of git.astron.nl:rtsd/hdlRTSD-209: tech_memory_ram_crwk_crw - For agilex 7 (agi027_xxxx) is also the ip_agi027_xxxx_ram_rw_rw added, but it is only supporting clock_b and a ratio of 1 . Added library ip_agi027_xxxx_ram_lib. So it can be used in the diag_databuffer.Fix 'can be created -> can be used'.