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  • HPR-158
  • L2SDP-1082
  • L2SDP-LIFT
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Created with Raphaël 2.2.07Nov62131Oct26252423222019171611109543228Sep272625212019181413126531Aug3029282524222118171615141098731Jul27262565427Jun2115141312752125May242317151110982126Apr25201817117654331Mar3028272322212017161514107227Feb242322211716159872131Jan27252423191716131211109322Dec2120191513Updated information header e.g: including a remark with an explanation for the modification of the file. Due to that the crwk_crw IP is unavailable for Agilex 7 modified this file to be also compatible with Agilex 7. The modification is based on the architecture of common_ram_crw_crw_ratio.vhd.Removed unnecessary carriage return.Fix missing 't' character in entityChanged the remark from 'See common_paged_ram_crw_crw for details' to 'See common_paged_ram_rw_rw for details', because it uses common_paged_ram_rw_rw and that one is changed. And changed next_page_* to *_next_page.Created new testbenches based on the architecture of tb_common_paged_ram_crw_crw.vhd, as common_paged_ram_cr_cw and common_paged_ram_rw_rw no longer uses underlying common_paged_ram_crw_crw.Commented out just added tb_common_paged_ram_ww_rr to regression_test_vhdl due to tb_tb_common_paged_ram_ww_rr was also added.Added src/vhdl/common_paged_ram_cr_cw.vhd to synth_files. Added tb/vhdl/tb_common_paged_ram_cr_cw.vhd and tb/vhdl/tb_common_paged_ram_rw_rw.vhd to test_bench_files. Added tb/vhdl/tb_common_paged_ram_cr_cw.vhd, tb/vhdl/tb_common_paged_ram_rw_rw.vhd and tb_common_paged_ram_ww_rr.vhd to regression_test_vhdl.Updated information header with the notification that it is unavailable for the Intel Agilex 7.Updated information header with the notification that it is unavailable for the Intel Agilex 7.Created new synth file based on tech_memory_ram_crwk_crw.vhd and tech_memory_ram_cr_cw.vhd, because the Agilex 7 is not supporting the crwk_crw variant as used for the previous device types. For them the generics and ports similar to common_ram_cr_cw_ratio.vhd and ip_agi027_ram_crk_cw.vhd are provided. Updated information header with remark and reference.Fix missing '>' character for -- enable_force_to_zeroAdded tech_memory_ram_crk_cw.vhd to synth_files.Added component description for ip_agi027_xxxx_ram_crk_cw.Updated information header. Modified to be compatible with Agilex 7. The modification is based on the architecture of common_ram_crw_crw.vhd.Created to be compatible with Agilex 7. Copied common_paged_ram_crw_crw.vhd and modified it based on the entity ports of common_ram_cr_cw.vhd. Replaced information header and added purpose, description, remarks and reference.Updated information header e.g.: Changed the remark 'See common_paged_ram_crw_crw for details' to referenced details, because crw_crw is unavailable for Agilex 7 it is illogical to refer to the crw_crw file. Modified to be compatible with Agilex 7. The modification is based on the architecture of common_paged ram_crw_crw.vhd.Updated information header. Modified to be compatible with Agilex 7. The modification is based on the architecture of common_ram_crw_crw.vhd. Changed the use of tech_memory_ram_cr_cw to tech_memory_ram_r_w for gen_simple_dual_port.Updated information header with the notification that it is unavailable for the Intel Agilex 7.Copied the ip_arria10_e2sg/ram/ip_arria10_e2sg_<ram_name>.vhd file and copied in the component declaration and instance example from generated/ram_2port_2040/sim/ip_agi027_xxxx_ram_<ram_name>_ram_2port_2040_<generated_hash>.vhd. Updated information header. Changed the technology_name from ip_arria10_e2sg to ip_agi027_xxxx. Checked the differences between the underlying files where the original vhd file is based on. There are no significant differences. Most of the parameters that are different are added and commented out.Updated information header. Added component descriptions for agi027_xxxx: ip_agi027_xxxx_ram_cr_cw, ip_agi027_xxxx_ram_rw_rw, ip_agi027_xxxx_ram_r_w and a notification for the components ip_agi027_xxxx_ram_crwk_crw and ip_agi027_xxxx_ram_crw_crw.Created new synth file by copying the tech_memory_ram_crw_crw, because the Agilex 7 is not supporting the crw_crw variant as used for the previous device types. For them the same clock is providing twice.Updated information header. Added remark that this one is not available for the Agilex 7.Updated information header. Added library ip_agi027_xxxx_ram_lib; Added generate-block for the agi027_xxxx. For r_w added g_rd_latency.Added the library to hdl_lib_uses_synth for the ip_agi027_xxxx. Added ip_agi027_xxxx_ram ip_agi027_xxxx_ram_lib to hdl_lib_disclose_library_clause_names. Added tech_memory_ram_rw_rw.vhd to synth_files.Copied from ip_arria10_e2sg/ram/. Changed technology name to ip_ agi027_xxxx for hdl_lib_name, hdl_library_clause_name, hdl_lib_uses_synth, hdl_lib_technology and synth_files, and in synth_files= *true_dual_port_ram_dual_clock.vhd to *true_dual_port_ram_single_clock.vhd.Create new IPs with (almost) the same configuration as the ip_arria10_es2g_ram_<ram_name>.ip. The version for the arria10_e2sg is 20.0.0 and for the agi027_xxxx is 20.4.0. The ram_name crw_crw and crwk_crw are not created, because Agilex isn't supporting this variants. The ram_name rw_rw is created in stead of crw_crw. The ram_name rw_rw is based on the ram_name crw_crw.Edited missing or wrong charactersCopied from ip_arria10_e2sg/ram/. Updated information header. Changed technology_name to agi027_xxxx. The copied ip_arria10_e2sg_true_dual_port_ram_dual_clock.vhd is changed for agi027_xxxx to a true dual port ram single clock, because the Agilex isn't supporting that variant.Recorver information header purpose FIFO -> RAMAdd missing g_use_complex condition.ip_agi027_xxxx/ram/ip_agi027_xxxx_ram_cr_cw.vhd: Copied the ip_arria10_e2sg/ram/ip_arria10_e2sg_<ram_name>.vhd file and copied in the component declaration and instance example from generated/ram_2port_2040/sim/ip_agi027_xxxx_ram_cr_cw_ram_2port_2040_cmcw2dy.vhd. Updated information header. Changed the technology_name from ip_arria10_e2sg to ip_agi027_xxxx. Checked the differences between the underlying files where the original vhd file is based on. There are no significant differences. Most of the parameters that are different are added and commented out.Merge branch 'RTSD-180' into 'master'Merge branch 'master' into RTSD-180The README is fully adapted for the Agilex 7 and the most important results of the synthesis are reported.Copied the ip_arria10_e2sg/fifo/ip_arria10_e2sg_<fifo_name>.vhd files. Updated information header. Changed the technology_name from ip_arria10_e2sg to ip_agi027_xxxx. Checked the differences between the underlying files where the original vhd file is based on. There are no significant differences. The parameters that are different are added and commented out. For <fifo_name>=dc_mixed_widths: In the range specification of std_logic_vectors within component ports, used_port'range is employed. However, for quicker referencing, it is preferable to specify the range in the same manner as with entity ports.Create new IP's with the same configuration as the ip_arria10_e2sg_fifo_<fifo_name>.ip. The only difference is that it is a newer version. The version for the arria10_e2sg is 19.1.0 and for the agi027_xxxx is 19.2.1.Copied from ip_arria10_e2sg/fifo/hdllib.cfg. Changed the technology_name from ip_arria10 to ip_agi027_xxxx for hdl_lib_name, hdl_library_clause_name, hdl_lib_technology, synth_files. Removed the IPs under qsys-generate_ip_libs.Updated information header. Added library ip_agi027_xxxx_fifo_lib; Added generate-block inclusive instantiation of module for the agi027_xxxxUpdated information header to recent standard. Added component descriptions for agi027_xxxx: ip_agi027_xxxx_fifo_sc, ip_agi027_xxxx_fifo_dc, ip_agi027_xxxx_fifo_dc_mixed_widths.Added the library to hdl_lib_uses_synth for the ip_agi027_xxxx. Added ip_agi027_xxxx_fifo ip_agi027_xxxx_fifo_lib to hdl_lib_disclose_library_clause_names.