Reinier van der Walle
--- a/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd 0 → 100644
+++ b/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd 0 → 100644
+                        
+    output_sosi_arr     : OUT t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0)    -- selected complex output with flow control
+  );
+END reorder_col_wide_select;
+
+ARCHITECTURE str OF reorder_col_wide_select IS
+
+  SIGNAL col_select_miso_arr : t_mem_miso_arr(g_nof_inputs-1 DOWNTO 0);
+
+BEGIN
+
+  col_select_miso <= col_select_miso_arr(0); -- All inputs have the same mosi/miso
+
+  ---------------------------------------------------------------
+  -- INSTANTIATE MULTIPLE SINGLE CHANNEL SUBBAND SELECT UNITS
+  ---------------------------------------------------------------
--- a/libraries/base/reorder/src/vhdl/reorder_col_select.vhd 0 → 100644
+++ b/libraries/base/reorder/src/vhdl/reorder_col_select.vhd 0 → 100644
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author : R vd Walle
+-- Purpose: Reorder packet
--- a/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd 0 → 100644
+++ b/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd 0 → 100644
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author : R vd Walle
+-- Purpose: Select and/or reorder data on multiple streams. 
+--
+-- Description:
+--   Reorder-col unit that handles a stream that consists of
--- a/libraries/base/reorder/src/vhdl/reorder_row_select.vhd 0 → 100644
+++ b/libraries/base/reorder/src/vhdl/reorder_row_select.vhd 0 → 100644
+    clk        => dp_clk,
+    in_data    => reorder_in_dat, 
+    in_select  => in_select, 
+    out_data   => reorder_out_dat
+  );  
+
+       
+  ---------------------------------------------------------------
+  -- REGISTERING AND PIPELINING
+  --
+  -- This process takes care of registering the incoming SOSI
+  -- array and the pipelining for all SOSI control fields. 
+  -- Also the data-output of the select_m_symbols block is merged
+  -- here with the rest of the pipelined SOSI signals.
+  ---------------------------------------------------------------
+   comb : PROCESS(r, input_sosi_arr, reorder_out_dat)
--- a/libraries/base/reorder/src/vhdl/reorder_row_select.vhd 0 → 100644
+++ b/libraries/base/reorder/src/vhdl/reorder_row_select.vhd 0 → 100644
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author : R vd Walle
+-- Purpose: Subband Select Reordering. 
+--
+-- Description: For every clock cycle within a frame a different output
+--              configuration can be created, based on the available inputs. 
+--
+--              The in_select input defines the mapping of the inputs to the outputs 
+--              for a single clock cylce.  
+--   
+-- Remarks:
+-- in_select has to be defined 1 clock cycle after the in_sosi data. 
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd 0 → 100644
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd 0 → 100644
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author : R vd Walle
+-- Usage:
+-- > as 10
+-- > run -all
+-- . Observe in_sosi_arr and out_sosi_arr in the Wave window
+--
+-- Description:
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd 0 → 100644
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd 0 → 100644
+-- > as 10
+-- > run -all
+-- . Observe in_sosi_arr and out_sosi_arr in the Wave window
+--
+-- Description:
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
+USE common_lib.common_lfsr_sequences_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE dp_lib.tb_dp_pkg.ALL;
+
+ENTITY tb_reorder_col_wide_row_select IS