initial commit of dp_sync_insert_v2

Closes L2SDP-281

libraries/base/dp/src/vhdl/dp_sync_insert_v2.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author : R vd Walle
+-- Purpose : * Insert extra sync pulses. 
+-- Description:
+--   Every nof_blk_per_sync block a sync pulse is created at the output. The block
+--   counter resets if a sync arrives at the input or when nof_blk_per_sync is reached.
+--   nof_blk_per_sync is controllable using M&C.
+--
+-- Remarks:
+-- . There is no support for back pressure. 
+-- . It does not compensate for missing data or extra data. There is NO reset function. It assumes that the 
+--   incoming data is perfectly aligned. Use a dp_sync_checker to assure the incoming data is perfect.      
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE work.dp_stream_pkg.ALL; 
+
+ENTITY dp_sync_insert_v2 IS
+  GENERIC (
+    g_nof_streams          : NATURAL := 1;
+    g_nof_blk_per_sync     : NATURAL := 200000;
+    g_nof_blk_per_sync_min : NATURAL := 19530
+  );             
+  PORT (    
+
+    -- Clocks and reset
+    mm_rst     : IN  STD_LOGIC;  
+    mm_clk     : IN  STD_LOGIC;
+    dp_rst     : IN  STD_LOGIC;
+    dp_clk     : IN  STD_LOGIC;
+    
+    -- MM bus access in memory-mapped clock domain
+    reg_mosi   : IN  t_mem_mosi := c_mem_mosi_rst;
+    reg_miso   : OUT t_mem_miso := c_mem_miso_rst;
+     
+    -- Streaming sink
+    in_sosi_arr : IN  t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+    -- Streaming source
+    out_sosi_arr: OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0)
+
+  );
+END dp_sync_insert_v2;
+
+
+ARCHITECTURE rtl OF dp_sync_insert_v2 IS
+
+  TYPE t_reg IS RECORD  -- local registers
+    blk_cnt          : NATURAL RANGE 0 TO g_nof_blk_per_sync;
+    nof_blk_per_sync : NATURAL RANGE 0 TO g_nof_blk_per_sync;
+    out_sosi_arr     : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+  END RECORD;
+  
+  CONSTANT c_reg_rst  : t_reg := ( 0, 0, (OTHERS => c_dp_sosi_rst));
+  CONSTANT c_mm_reg_w : NATURAL := ceil_log2(g_nof_blk_per_sync+1);
+  CONSTANT c_nof_blk_per_sync_mm_reg   : t_c_mem := (1, 1, c_mm_reg_w, 1, 'X');
+  CONSTANT c_init_reg : STD_LOGIC_VECTOR(c_mem_reg_init_w-1 DOWNTO 0) := TO_UVEC(g_nof_blk_per_sync, c_mem_reg_init_w);
+
+  -- Define the local registers in t_reg record
+  SIGNAL r         : t_reg;
+  SIGNAL nxt_r     : t_reg;
+
+  SIGNAL reg_nof_blk_per_sync : STD_LOGIC_VECTOR(c_mm_reg_w -1 DOWNTO 0);
+  
+BEGIN
+  
+  out_sosi_arr <= r.out_sosi_arr;
+  
+  p_clk : PROCESS(dp_rst, dp_clk)
+  BEGIN
+    IF dp_rst='1' THEN
+      r <= c_reg_rst;
+    ELSIF rising_edge(dp_clk) THEN
+      r <= nxt_r;
+    END IF;
+  END PROCESS;  
+
+  p_comb : PROCESS(r, in_sosi_arr, reg_nof_blk_per_sync)
+    VARIABLE v : t_reg;
+  BEGIN
+    v := r;
+    v.out_sosi_arr := in_sosi_arr;
+
+    v.nof_blk_per_sync := TO_UINT(reg_nof_blk_per_sync);
+    IF TO_UINT(reg_nof_blk_per_sync) < g_nof_blk_per_sync_min THEN
+      v.nof_blk_per_sync := g_nof_blk_per_sync_min;
+    END IF;
+
+    IF in_sosi_arr(0).sop = '1' THEN
+      v.blk_cnt  := r.blk_cnt + 1;        
+      
+      IF r.blk_cnt = r.nof_blk_per_sync-1 OR in_sosi_arr(0).sync = '1' THEN
+        v.blk_cnt := 0;
+        FOR I IN 0 TO g_nof_streams-1 LOOP
+          v.out_sosi_arr(I).sync := '1';
+        END LOOP;   
+      END IF; 
+    END IF; 
+  
+    nxt_r <= v;
+  END PROCESS;  
+
+
+  u_common_reg_r_w_dc : ENTITY common_lib.common_reg_r_w_dc
+  GENERIC MAP (
+    g_cross_clock_domain => TRUE,
+    g_readback           => FALSE,
+    g_reg                => c_nof_blk_per_sync_mm_reg,
+    g_init_reg           => c_init_reg
+  )
+  PORT MAP (
+    -- Clocks and reset
+    mm_rst         => mm_rst,
+    mm_clk         => mm_clk,
+    st_rst         => dp_rst,
+    st_clk         => dp_clk,
+    
+    -- Memory Mapped Slave in mm_clk domain
+    sla_in         => reg_mosi,
+    sla_out        => reg_miso,
+    
+    -- MM registers in st_clk domain
+    reg_wr_arr     => OPEN,
+    reg_rd_arr     => OPEN,
+    in_reg         => reg_nof_blk_per_sync,
+    out_reg        => reg_nof_blk_per_sync 
+  );
+
+END rtl;