Reinier van der Walle · Reinier van der Walle · Eric Kooistra
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_scale.vhd 0 → 100644
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_scale.vhd 0 → 100644
+
+  CONSTANT c_mm_clk_period              : TIME := 20 ns;
+  CONSTANT c_dp_clk_period              : TIME := 10 ns;
+  CONSTANT c_cross_clock_domain_latency : NATURAL := 20;
+ 
+  CONSTANT c_complex_data : BOOLEAN := TRUE; 
+  CONSTANT c_complex_gain : BOOLEAN := FALSE;
+  CONSTANT c_gain_w       : NATURAL := 8;  
+  CONSTANT c_in_dat_w     : NATURAL := 9; 
+  CONSTANT c_in_length    : INTEGER :=  2**(c_in_dat_w-3)-1; -- Expected sosi does not take clipping into account
+  CONSTANT c_in_max       : INTEGER :=  2**(c_in_dat_w-3)-1;
+  CONSTANT c_in_min       : INTEGER := -2**(c_in_dat_w-3);
+  CONSTANT c_out_dat_w    : NATURAL := c_in_dat_w;  -- skip double sign bit and assume complex gain amplitude <= 1
+  cONSTANT c_lsb_w        : NATURAL := 1;  
+
+  CONSTANT c_gain_re      : INTEGER := 2**2;