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Add missing re and im values to v_last. Used in...

Merged Eric Kooistra requested to merge L2SDP-960b into master
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@@ -174,15 +174,20 @@ begin
@@ -174,15 +174,20 @@ begin
-- Determine and keep last expected sosi field values after end of stimuli
-- Determine and keep last expected sosi field values after end of stimuli
-- . e_qual
-- . e_qual
v_last.bsn := std_logic_vector( unsigned(g_bsn_init) + g_nof_repeat - 1);
v_last.bsn := std_logic_vector( unsigned(g_bsn_init) + g_nof_repeat - 1);
v_last.channel := TO_DP_CHANNEL(g_channel_init + (g_nof_repeat - 1) * g_channel_incr);
v_last.channel := TO_DP_CHANNEL(g_channel_init + (g_nof_repeat - 1) * g_channel_incr);
v_last.err := TO_DP_ERROR(g_err_init + (g_nof_repeat - 1) * g_err_incr);
v_last.err := TO_DP_ERROR(g_err_init + (g_nof_repeat - 1) * g_err_incr);
-- . account for g_pkt_len
-- . account for g_pkt_len
v_last.data := INCR_UVEC(v_sosi.data, g_pkt_len - 1);
v_last.data := INCR_UVEC(v_sosi.data, g_pkt_len - 1);
v_last.data := RESIZE_DP_DATA(v_last.data(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w
v_last.data := RESIZE_DP_DATA(v_last.data(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w
 
v_last.re := INCR_UVEC(v_sosi.re, g_pkt_len - 1);
 
v_last.re := RESIZE_DP_DSP_DATA(v_last.re(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w
 
v_last.im := INCR_UVEC(v_sosi.im, g_pkt_len - 1);
 
v_last.im := RESIZE_DP_DSP_DATA(v_last.im(g_in_dat_w - 1 downto 0)); -- wrap when >= 2**g_in_dat_w
last_snk_in <= v_last;
last_snk_in <= v_last;
-- Signal end of stimuli
-- Signal end of stimuli
proc_common_wait_some_cycles(clk, g_wait_last_evt); -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
-- . latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
 
proc_common_wait_some_cycles(clk, g_wait_last_evt);
proc_common_gen_pulse(clk, last_snk_in_evt);
proc_common_gen_pulse(clk, last_snk_in_evt);
proc_common_wait_some_cycles(clk, 50);
proc_common_wait_some_cycles(clk, 50);
tb_end <= '1';
tb_end <= '1';
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