Resolve L2SDP-18

Closes L2SDP-18

libraries/base/dp/src/vhdl/dp_calculate_crc.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-- Author: E. Kooistra
+-- Date: 17 April 2023
+-- Purpose: Calculate CRC per block of data
+-- Description:
+--   The calculated blk_crc of a block is available immediately after the
+--   snk_in.eop of that block.
+
+LIBRARY IEEE, common_lib, easics_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+
+USE easics_lib.PCK_CRC8_D8.ALL;
+USE easics_lib.PCK_CRC16_D16.ALL;
+USE easics_lib.PCK_CRC28_D28.ALL;
+USE easics_lib.PCK_CRC32_D32.ALL;
+USE easics_lib.PCK_CRC32_D64.ALL;
+
+
+ENTITY dp_calculate_crc IS
+  GENERIC (
+    g_data_w  : NATURAL := 32;
+    g_crc_w   : NATURAL := 32
+  );
+  PORT (
+    rst          : IN  STD_LOGIC;
+    clk          : IN  STD_LOGIC;
+    -- ST sink
+    snk_in       : IN  t_dp_sosi;
+    blk_crc      : OUT STD_LOGIC_VECTOR(g_crc_w-1 DOWNTO 0)
+  );
+END dp_calculate_crc;
+
+
+ARCHITECTURE rtl OF dp_calculate_crc IS
+
+  CONSTANT c_crc_init : STD_LOGIC_VECTOR(g_crc_w-1 DOWNTO 0) := (OTHERS=>'1');
+  
+  FUNCTION func_next_crc(data, crc : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
+    VARIABLE v_crc : STD_LOGIC_VECTOR(g_crc_w-1 DOWNTO 0) := c_crc_init;
+  BEGIN
+    IF    g_data_w =  8 AND g_crc_w =  8 THEN v_crc := nextCRC8_D8(data, crc);
+    ELSIF g_data_w = 16 AND g_crc_w = 16 THEN v_crc := nextCRC16_D16(data, crc);
+    ELSIF g_data_w = 28 AND g_crc_w = 28 THEN v_crc := nextCRC28_D28(data, crc);
+    ELSIF g_data_w = 32 AND g_crc_w = 32 THEN v_crc := nextCRC32_D32(data, crc);
+    ELSIF g_data_w = 64 AND g_crc_w = 32 THEN v_crc := nextCRC32_D64(data, crc);
+    ELSE
+      REPORT "Data width and CRC width combination not supported (yet)" SEVERITY FAILURE;
+    END IF;
+    RETURN v_crc;
+  END func_next_crc;
+
+  SIGNAL data         : STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
+  SIGNAL calc_crc     : STD_LOGIC_VECTOR(g_crc_w-1 DOWNTO 0);
+  SIGNAL nxt_calc_crc : STD_LOGIC_VECTOR(g_crc_w-1 DOWNTO 0);
+  SIGNAL i_blk_crc    : STD_LOGIC_VECTOR(g_crc_w-1 DOWNTO 0);
+  SIGNAL nxt_blk_crc  : STD_LOGIC_VECTOR(g_crc_w-1 DOWNTO 0);
+
+BEGIN
+
+  data <= snk_in.data(g_data_w-1 DOWNTO 0);
+
+  blk_crc <= i_blk_crc;
+
+  p_clk : PROCESS(rst, clk)
+  BEGIN
+    IF rst='1' THEN
+      calc_crc   <= c_crc_init;
+      i_blk_crc  <= c_crc_init;
+    ELSIF rising_edge(clk) THEN
+      calc_crc   <= nxt_calc_crc;
+      i_blk_crc  <= nxt_blk_crc;
+    END IF;
+  END PROCESS;
+
+  p_crc : PROCESS(data, calc_crc, i_blk_crc, snk_in)
+    VARIABLE v_crc : STD_LOGIC_VECTOR(g_crc_w-1 DOWNTO 0);
+  BEGIN
+    v_crc := func_next_crc(data, calc_crc);
+
+    -- Calculate CRC per block
+    nxt_calc_crc <= calc_crc;
+    IF snk_in.sop = '1' THEN  -- restart CRC at begin of block
+      nxt_calc_crc <= func_next_crc(data, c_crc_init);
+    ELSIF snk_in.valid = '1' THEN  -- calculate CRC during block
+      nxt_calc_crc <= v_crc;
+    END IF;
+
+    -- Hold CRC of previous block, available after eop
+    nxt_blk_crc <= i_blk_crc;
+    IF snk_in.eop = '1' THEN
+      nxt_blk_crc <= v_crc;
+    END IF;
+  END PROCESS;
+
+END rtl;