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Resolve L2SDP-667

Merged Resolve L2SDP-667
L2SDP-667 into master
2 unresolved threads
Merged Job van Wee requested to merge L2SDP-667 into master
2 unresolved threads
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applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+ 31
− 30
@@ -50,8 +50,9 @@ ENTITY ddrctrl IS
g_sim_model : BOOLEAN := TRUE; -- determens if this is a simulation
g_technology : NATURAL := c_tech_select_default;
g_nof_streams : NATURAL := 12; -- number of input streams
g_data_w : NATURAL := 14 -- data with of input data vectors
);
g_data_w : NATURAL := 14; -- data with of input data vectors
g_stop_percentage : NATURAL := 50
);
PORT (
clk : IN STD_LOGIC := '0';
rst : IN STD_LOGIC;
@@ -59,8 +60,7 @@ ENTITY ddrctrl IS
mm_rst : IN STD_LOGIC := '0';
in_sosi_arr : IN t_dp_sosi_arr; -- input data
wr_not_rd : IN STD_LOGIC := '0';
out_of : OUT NATURAL; -- amount of internal overflow this output
out_adr : OUT NATURAL;
stop_in : IN STD_LOGIC := '0';
term_ctrl_out : OUT t_tech_ddr3_phy_terminationcontrol;
@@ -85,40 +85,20 @@ ARCHITECTURE str OF ddrctrl IS
CONSTANT c_io_ddr_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr );
CONSTANT c_wr_fifo_depth : NATURAL := 256; -- defined at DDR side of the FIFO, >=16 and independent of wr burst size, default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
CONSTANT c_rd_fifo_depth : NATURAL := 256; -- defined at DDR side of the FIFO, >=16 AND > max number of rd burst sizes (so > c_rd_fifo_af_margin), default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
CONSTANT c_burstsize : NATURAL := 64; -- max burstsize for max troughput
CONSTANT c_bitshift_adr : NATURAL := ceil_log2(c_burstsize);
CONSTANT c_adr_w : NATURAL := func_tech_ddr_ctlr_address_w( g_tech_ddr ); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
CONSTANT c_max_adr : NATURAL := 2**(c_adr_w)-1; -- the maximal address that is possible within the vector length of the address
CONSTANT c_zeros : STD_LOGIC_VECTOR(c_bitshift_adr-1 DOWNTO 0) := (OTHERS => '0');
-- signals for connecting the components
SIGNAL adr : NATURAL := 0;
SIGNAL ctrl_clk : STD_LOGIC;
SIGNAL ctrl_rst : STD_LOGIC;
SIGNAL out_of : NATURAL := 0;
SIGNAL out_sosi : t_dp_sosi := c_dp_sosi_init;
SIGNAL out_adr : NATURAL := 0;
SIGNAL dvr_mosi : t_mem_ctlr_mosi := c_mem_ctlr_mosi_rst;
SIGNAL wr_sosi : t_dp_sosi := c_dp_sosi_init;
SIGNAL rd_siso : t_dp_siso := c_dp_siso_rst;
SIGNAL dvr_mosi : t_mem_ctlr_mosi;
BEGIN
p_burst : PROCESS(adr)
BEGIN
IF TO_UVEC(adr, c_adr_w)(c_bitshift_adr-1 DOWNTO 0) = c_zeros THEN
dvr_mosi.burstbegin <= '1';
IF adr = 0 THEN
dvr_mosi.address <= TO_UVEC(c_max_adr-c_burstsize, dvr_mosi.address'length);
ELSE
dvr_mosi.address <= TO_UVEC(adr-c_burstsize, dvr_mosi.address'length);
END IF;
ELSE
dvr_mosi.burstbegin <= '0';
END IF;
END PROCESS;
dvr_mosi.burstsize <= TO_UVEC(c_burstsize, dvr_mosi.burstsize'length);
dvr_mosi.wr <= wr_not_rd;
dvr_mosi.rd <= NOT wr_not_rd;
-- input to io_ddr
u_ddrctrl_input : ENTITY work.ddrctrl_input
@@ -133,8 +113,8 @@ BEGIN
rst => rst,
in_sosi_arr => in_sosi_arr,
out_of => out_of,
out_sosi => wr_sosi,
out_adr => adr
out_sosi => out_sosi,
out_adr => out_adr
);
-- functions as a fifo buffer for input data into the sdram stick. also manages input to sdram stick.
@@ -211,4 +191,25 @@ BEGIN
phy4_ou => phy4_ou
);
-- controller of ddrctrl
u_ddrctrl_controller : ENTITY work.ddrctrl_controller
GENERIC MAP(
g_tech_ddr => g_tech_ddr,
g_stop_percentage => g_stop_percentage
)
PORT MAP(
clk => clk,
rst => rst,
inp_of => out_of,
inp_sosi => out_sosi,
inp_adr => out_adr,
dvr_mosi => dvr_mosi,
wr_sosi => wr_sosi,
rd_siso => rd_siso,
stop_in => stop_in
);
END str;