Resolve L2SDP-88

Review L2SDP-88

libraries/dsp/st/src/vhdl/st_histogram_8_april.vhd

@@ -204,8 +204,8 @@ BEGIN
     out_dat => rd_cnt_allowed_pp
   );
   
-  -- Detect a (valid) repeating address seperated by one other address past the initialisation and outside the first two cycles of a (new) sync
-  toggle_detect  <= snk_in.valid WHEN (bin_reader_mosi_pp.address = bin_reader_mosi.address AND bin_reader_mosi_pp.address /= prev_bin_reader_mosi.address AND toggle_detect_false = '0' AND (snk_in.sync='0' OR dp_pipeline_src_out_p.sync='0') ) 
+  -- Detect a (valid) repeating address seperated by one other address past the initialisation and outside the first two cycles of a (new) sync                                        --also @sync, one wil be true; use  NOT(1 or 1) instead of (0 or 0)
+  toggle_detect  <= snk_in.valid WHEN (bin_reader_mosi_pp.address = bin_reader_mosi.address AND bin_reader_mosi_pp.address /= prev_bin_reader_mosi.address AND toggle_detect_false = '0' AND NOT(snk_in.sync='1' OR dp_pipeline_src_out_p.sync='1') ) 
                                  ELSE '0';
 
   
@@ -246,7 +246,7 @@ BEGIN
   -- . out : bin_writer_mosi  (latency: 3)
   -----------------------------------------------------------------------------
   p_nxt_bin_writer_mosi : PROCESS(common_ram_r_w_0_miso, common_ram_r_w_0_miso.rdval, common_ram_r_w_0_miso.rddata, 
-                                  bin_reader_mosi_pp.address, toggle_detect, rd_cnt_allowed_pp, init_phase, prev_wrdata, prev_prev_wrdata, sync_detect_pp, same_r_w_address_pp, dp_pipeline_src_out_pp.valid) IS -- dp_pipeline_src_out_pp necesary??
+                                  bin_reader_mosi_pp.address, toggle_detect_pp, rd_cnt_allowed_pp, init_phase, prev_wrdata, prev_prev_wrdata, prev_prev_prev_wrdata, sync_detect_pp, same_r_w_address_pp, dp_pipeline_src_out_pp.valid) IS -- dp_pipeline_src_out_pp necesary??
   BEGIN
     nxt_bin_writer_mosi <= c_mem_mosi_rst;
     dbg_state_string <= "unv";
@@ -257,7 +257,7 @@ BEGIN
       nxt_prev_wrdata             <= TO_UINT(common_ram_r_w_0_miso.rddata) + 1;
       dbg_state_string <= "val";
 
-    ELSIF toggle_detect_pp = '1' THEN                                                       -- Mist is sensitivity list !
+    ELSIF toggle_detect_pp = '1' THEN
       nxt_bin_writer_mosi.wr      <= '1';
       nxt_bin_writer_mosi.wrdata  <= TO_UVEC( (prev_prev_wrdata+1), c_mem_data_w);
       nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
@@ -280,7 +280,7 @@ BEGIN
       
     ELSIF same_r_w_address_pp = '1' THEN
       nxt_bin_writer_mosi.wr      <= '1';
-      nxt_bin_writer_mosi.wrdata  <= TO_UVEC( (prev_prev_prev_wrdata+1), c_mem_data_w);       -- Misses in sensitivity list !
+      nxt_bin_writer_mosi.wrdata  <= TO_UVEC( (prev_prev_prev_wrdata+1), c_mem_data_w);
       nxt_bin_writer_mosi.address <= bin_reader_mosi_pp.address;
       nxt_prev_wrdata             <= prev_prev_prev_wrdata + 1;
       dbg_state_string  <= "srw";
@@ -312,9 +312,9 @@ BEGIN
   -- .     : bin_arbiter_wr_mosi (latency: 4)
   -----------------------------------------------------------------------------
   nxt_bin_arbiter_wr_mosi <= bin_writer_mosi;
-  -- Read RAM when subsequent addresses are not the same, when there is no toggle detected and only when the same address is not going to be written to
-  nxt_bin_arbiter_rd_mosi.rd <= bin_reader_mosi.rd WHEN (bin_reader_mosi.address /= prev_bin_reader_mosi.address AND bin_reader_mosi.address /= bin_reader_mosi_pp.address AND NOT(bin_reader_mosi.address = bin_reader_mosi_ppp.address) ) 
-                                                         -- AND sync_detect='0')                                                                                  -- activate sync !
+  -- Read RAM when subsequent addresses are not the same, when there is no toggle detected and only when the same address is not going to be written to. When a sync is detected don't read in the old RAM block.
+  nxt_bin_arbiter_rd_mosi.rd <= bin_reader_mosi.rd WHEN (bin_reader_mosi.address /= prev_bin_reader_mosi.address AND bin_reader_mosi.address /= bin_reader_mosi_pp.address 
+                                                         AND NOT(bin_reader_mosi.address = bin_reader_mosi_ppp.address) AND sync_detect='0')
                                                    OR (init_phase = '1') ELSE '0';
   nxt_bin_arbiter_rd_mosi.address <= bin_reader_mosi.address;
 
@@ -328,6 +328,9 @@ BEGIN
       bin_arbiter_rd_mosi <= nxt_bin_arbiter_rd_mosi;
     END IF;
   END PROCESS;
+  
+  -- Temporary debug data
+  ram_miso.rddata <= bin_arbiter_wr_mosi.wrdata;
 
 
   -----------------------------------------------------------------------------