Added g_sepa_switch_en to support mitigation of quantization noise crosstalk...

Added g_sepa_switch_en to support mitigation of quantization noise crosstalk between two real inputs.

Closes L2SDP-440

libraries/base/common/src/vhdl/common_create_strobes_from_valid.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Author: Eric Kooistra
+-- Purpose: Create sync interval by counting input valids
+-- Description:
+--
+--  The first out_sync is created at the first inval after rst release. The
+--  subsequent out_sync are created every m in_val, at the start of a block.
+--
+--    n = g_nof_clk_per_block
+--    m = g_nof_clk_per_sync
+--                _____________________________________________________
+--    in_val   __|
+--
+--    blk_cnt    |    0    |    1    |    2    |    3    |    4    |
+--
+--    val_cnt    |0        |n        |n*2      |n*3 - m  |         |0
+--                _                       _                         _
+--    out_sync __| |_____________________| |_______________________| |_
+--                _____________________________________________________
+--    out_val  __|
+--                _         _         _         _         _         _
+--    out_sop  __| |_______| |_______| |_______| |_______| |_______| |_
+--                        _         _         _         _         _
+--    out_eop  __________| |_______| |_______| |_______| |_______| |___
+--
+-- Remark:
+-- . Use VHDL coding template from:
+--   https://support.astron.nl/confluence/display/SBe/VHDL+design+patterns+for+RTL+coding
+-- . The out_sop and out_eop are created as well, for reference.
+-- . The out_sync1 for LOFAR1 style is only avaiable if g_pipeline = TRUE,
+--   because the pipeline is needed to let the out_sync1 preceed the
+--   out_sop and other strobes.
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE work.common_pkg.ALL;
+
+ENTITY common_create_strobes_from_valid IS
+  GENERIC (
+    g_pipeline           : BOOLEAN := TRUE;
+    g_nof_clk_per_sync   : NATURAL := 200*10**6;
+    g_nof_clk_per_block  : NATURAL := 1024
+  );
+  PORT (
+    rst       : IN  STD_LOGIC := '0';
+    clk       : IN  STD_LOGIC;
+    in_val    : IN  STD_LOGIC;
+    out_val   : OUT STD_LOGIC;
+    out_sop   : OUT STD_LOGIC;
+    out_eop   : OUT STD_LOGIC;
+    out_sync  : OUT STD_LOGIC;  -- DP style: sync at sop
+    out_sync1 : OUT STD_LOGIC   -- LOFAR1 style: sync before sop
+  );
+END common_create_strobes_from_valid;
+
+
+ARCHITECTURE rtl OF common_create_strobes_from_valid IS
+
+  TYPE t_state IS RECORD  -- function state registers
+    val_cnt : NATURAL RANGE 0 TO g_nof_clk_per_sync-1;
+    blk_cnt : NATURAL RANGE 0 TO g_nof_clk_per_block-1;
+  END RECORD;
+
+  TYPE t_outputs IS RECORD  -- copy of entity outputs
+    out_val  : STD_LOGIC;
+    out_sop  : STD_LOGIC;
+    out_eop  : STD_LOGIC;
+    out_sync : STD_LOGIC;
+  END RECORD;
+
+  CONSTANT c_state_rst   : t_state := (val_cnt => 0, blk_cnt => 0);
+  CONSTANT c_outputs_rst : t_outputs := ('0', '0', '0', '0');
+
+  SIGNAL q : t_state := c_state_rst;  -- stored state with latency one
+  SIGNAL d : t_state := c_state_rst;  -- zero latency state
+
+  SIGNAL o : t_outputs := c_outputs_rst;  -- zero latency outputs
+  SIGNAL p : t_outputs := c_outputs_rst;  -- pipelined outputs
+
+BEGIN
+
+  -- p_state
+  q <= d WHEN rising_edge(clk);
+
+  p_comb : PROCESS(rst, q, in_val)
+    VARIABLE v : t_state;
+  BEGIN
+    -- Default
+    v := q;
+    o.out_val <= in_val;
+    o.out_sop <= '0';
+    o.out_eop <= '0';
+    o.out_sync <= '0';
+
+    -- Function
+    IF in_val = '1' THEN
+      -- maintain in_val counters
+      IF q.val_cnt >= g_nof_clk_per_sync-1 THEN
+        v.val_cnt := 0;
+      ELSE
+        v.val_cnt := v.val_cnt + 1;
+      END IF;
+      IF q.blk_cnt >= g_nof_clk_per_block-1 THEN
+        v.blk_cnt := 0;
+      ELSE
+        v.blk_cnt := v.blk_cnt + 1;
+      END IF;
+      -- create out_sop at start of block
+      IF q.blk_cnt = 0 THEN
+        o.out_sop <= '1';
+      END IF;
+      -- create out_eop at end of block
+      IF q.blk_cnt = g_nof_clk_per_block-1 THEN
+        o.out_eop <= '1';
+      END IF;
+      -- create out_sync at start of first block of sync interval
+      IF q.blk_cnt = 0 AND q.val_cnt < g_nof_clk_per_block THEN
+        o.out_sync <= '1';
+      END IF;
+    END IF;
+
+    -- Reset
+    IF rst = '1' THEN
+      v := c_state_rst;
+    END IF;
+
+    -- Result
+    d <= v;
+
+  END PROCESS;
+
+  -- Output
+  p <= o WHEN rising_edge(clk);
+
+  out_val  <= o.out_val  WHEN g_pipeline = FALSE ELSE p.out_val;
+  out_sop  <= o.out_sop  WHEN g_pipeline = FALSE ELSE p.out_sop;
+  out_eop  <= o.out_eop  WHEN g_pipeline = FALSE ELSE p.out_eop;
+  out_sync <= o.out_sync WHEN g_pipeline = FALSE ELSE p.out_sync;
+
+  out_sync1 <= '0' WHEN g_pipeline = FALSE ELSE o.out_sync;
+
+END rtl;