Resolve STAT-314

Closes STAT-314. To be continued on L2SDP-88

libraries/dsp/st/src/vhdl/mms_st_histogram.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+-- 
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+-- 
+--     http://www.apache.org/licenses/LICENSE-2.0
+-- 
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- 
+-- Author: J.W.E. Oudman
+-- Purpose: Create a histogram from the input data and present it to the MM bus
+-- Description: 
+--   mms_st_histogram couples the st_histogram component which works entirely
+--   in the dp clock domain through st_histogram_reg that handles the cross
+--   domain conversion to the MM bus.
+--
+--
+--             --------------------------------------
+--             | mms_st_histogram                   |
+--             |                                    |
+--             |   ----------------                 |         -------
+--   snk_in -->|-->| st_histogram |                 |             ^
+--             |   ----------------                 |             |
+--             |      |      ^                      |
+--             |      |      |                      |           dp clock domain
+--             |    ram_st_histogram_miso           |
+--             |      |      |                      |          
+--             |      |    ram_st_histogram_mosi    |             |
+--             |      v      |                      |             v
+--             | --------------------               |         -------
+--             | | st_histogram_reg |-- ram_miso -->|-->        mm clock domain
+--             | |                  |<-- ram_mosi --|<--
+--             | --------------------               |         -------
+--             |                                    |
+--             --------------------------------------
+--
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, mm_lib, technology_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+ENTITY mms_st_histogram IS
+  GENERIC (
+    g_in_data_w     : NATURAL := 14;   -- >= 9 when g_nof_bins is 512; (max. c_dp_stream_data_w =768)
+    g_nof_bins      : NATURAL := 512;  -- is a power of 2 and g_nof_bins <= c_data_span; max. 512
+    g_nof_data      : NATURAL;         -- 
+    g_str           : STRING  := "freq.density"  -- to select output to MM bus ("frequency" or "freq.density")
+  );                
+  PORT (            
+    dp_rst          : IN  STD_LOGIC;
+    dp_clk          : IN  STD_LOGIC;
+    mm_rst          : IN  STD_LOGIC;
+    mm_clk          : IN  STD_LOGIC;
+                    
+    -- Streaming    
+    snk_in      : IN  t_dp_sosi;
+
+    -- Memory Mapped
+    ram_mosi : IN  t_mem_mosi;
+    ram_miso : OUT t_mem_miso
+  );
+END mms_st_histogram;
+
+ARCHITECTURE str OF mms_st_histogram IS
+  
+  SIGNAL ram_st_histogram_mosi : t_mem_mosi;
+  SIGNAL ram_st_histogram_miso : t_mem_miso;
+  
+BEGIN 
+  
+  u_st_histogram : ENTITY work.st_histogram
+  GENERIC MAP(
+    g_in_data_w => g_in_data_w,
+    g_nof_bins  => g_nof_bins,
+    g_nof_data  => g_nof_data,
+    g_str       => g_str
+  )
+  PORT MAP (
+    dp_rst      => dp_rst,
+    dp_clk      => dp_clk,
+    
+    snk_in      => snk_in,
+    sla_in_ram_mosi    => ram_st_histogram_mosi,
+    sla_out_ram_miso    => ram_st_histogram_miso
+  );
+  
+  u_st_histogram_reg : ENTITY work.st_histogram_reg
+--  GENERIC MAP(
+--    g_in_data_w =>
+--    g_nof_bins  =>
+--    g_nof_data  =>
+--    g_str       =>
+--  )
+  PORT MAP (
+    dp_rst                => dp_rst,
+    dp_clk                => dp_clk,
+    mm_rst                => mm_rst,
+    mm_clk                => mm_clk,
+    
+    mas_out_ram_mosi => ram_st_histogram_mosi,
+    mas_in_ram_miso => ram_st_histogram_miso,
+    
+    ram_mosi              => ram_mosi,
+    ram_miso              => ram_miso
+  );
+  
+END str;