Replaced dp_fifo_fill_dc with dp_fifo_fill_eop in tr_10GbE

libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd

@@ -229,17 +229,18 @@ BEGIN
   );  
   
   ---------------------------------------------------------------------------------------
-  -- TX: FIFO: dp_clk -> tx_clk and with fill level so we can deliver packets to the MAC fast enough
+  -- TX: FIFO: dp_clk -> tx_clk and with fill level/eop trigger so we can deliver packets to the MAC fast enough
   ---------------------------------------------------------------------------------------
-  gen_dp_fifo_fill_dc : FOR i IN 0 TO g_nof_macs-1 GENERATE
-    u_dp_fifo_fill_dc : ENTITY dp_lib.dp_fifo_fill_dc
+  gen_dp_fifo_fill_eop : FOR i IN 0 TO g_nof_macs-1 GENERATE
+    u_dp_fifo_fill_eop : ENTITY dp_lib.dp_fifo_fill_eop
     GENERIC MAP (
-      g_technology  => g_technology,
-      g_data_w      => c_xgmii_data_w,
-      g_empty_w     => c_tech_mac_10g_empty_w,
-      g_use_empty   => TRUE,
-      g_fifo_fill   => g_tx_fifo_fill,
-      g_fifo_size   => g_tx_fifo_size
+      g_technology     => g_technology,
+      g_use_dual_clock => TRUE,
+      g_data_w         => c_xgmii_data_w,
+      g_empty_w        => c_tech_mac_10g_empty_w,
+      g_use_empty      => TRUE,
+      g_fifo_fill      => g_tx_fifo_fill,
+      g_fifo_size      => g_tx_fifo_size
     )
     PORT MAP (
       wr_rst      => dp_rst,