fixed bug in common_areset and synchronized reset signals in

ip_arria10_e1sg_jesd204b.vhd

Closes L2SDP-209

libraries/base/common/src/vhdl/common_areset.vhd

@@ -45,7 +45,7 @@ END;
 ARCHITECTURE str OF common_areset IS
  
   CONSTANT c_rst_level_n : STD_LOGIC := NOT g_rst_level;
-  
+  SIGNAL i_rst           : STD_LOGIC; 
 BEGIN
 
   -- When in_rst becomes g_rst_level then out_rst follows immediately (asynchronous reset apply).
@@ -55,13 +55,14 @@ BEGIN
   -- . g_rst_level = '0': output asynchronoulsy follows the falling edge input and synchronises the rising edge input.
   -- . g_rst_level = '1': output asynchronoulsy follows the rising edge input and synchronises the falling edge input.
   
+  i_rst <= NOT in_rst WHEN g_rst_level = '0' ELSE in_rst;
   u_async : ENTITY work.common_async
   GENERIC MAP (
     g_rst_level => g_rst_level,
     g_delay_len => g_delay_len
   )
   PORT MAP (
-    rst  => in_rst,
+    rst  => i_rst,
     clk  => clk,
     din  => c_rst_level_n,
     dout => out_rst