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updated yaml file for tech_jesd to include register at offset 0

Merged updated yaml file for tech_jesd to include register at offset 0
L2SDP-531 into master
Merged Reinier van der Walle requested to merge L2SDP-531 into master
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libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml
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@@ -42,6 +42,15 @@ peripherals:
mm_port_description: ""
number_of_mm_ports: g_nof_streams
fields:
- - {field_name: rx_lane_ctrl_common, mm_width: 3, bit_offset: 0, access_mode: RW, address_offset: 0x00}
- - {field_name: rx_lane_ctrl_0, mm_width: 3, bit_offset: 0, access_mode: RW, address_offset: 0x04}
- - {field_name: rx_lane_ctrl_1, mm_width: 3, bit_offset: 0, access_mode: RW, address_offset: 0x08}
- - {field_name: rx_lane_ctrl_2, mm_width: 3, bit_offset: 0, access_mode: RW, address_offset: 0x0C}
- - {field_name: rx_lane_ctrl_3, mm_width: 3, bit_offset: 0, access_mode: RW, address_offset: 0x10}
- - {field_name: rx_lane_ctrl_4, mm_width: 3, bit_offset: 0, access_mode: RW, address_offset: 0x14}
- - {field_name: rx_lane_ctrl_5, mm_width: 3, bit_offset: 0, access_mode: RW, address_offset: 0x18}
- - {field_name: rx_lane_ctrl_6, mm_width: 3, bit_offset: 0, access_mode: RW, address_offset: 0x1C}
- - {field_name: rx_lane_ctrl_7, mm_width: 3, bit_offset: 0, access_mode: RW, address_offset: 0x20}
- - {field_name: rx_dll_ctrl, mm_width: 17, bit_offset: 0, access_mode: RW, address_offset: 0x50}
- - {field_name: rx_syncn_sysref_ctrl, mm_width: 25, bit_offset: 0, access_mode: RW, address_offset: 0x54}
- - {field_name: rx_csr_lmfc_offset, mm_width: 8, bit_offset: 12, access_mode: RW, address_offset: 0x54}