Use v.busy, instead of r.busy, to allow start_pulse at mm_done, to support...

Use v.busy, instead of r.busy, to allow start_pulse at mm_done, to support zero gaps between output blocks.

Closes L2SDP-502

doc/erko_hdl_design_article.txt

@@ -111,10 +111,16 @@ Implementation steps:
     SIGNAL r             : t_reg;
     SIGNAL nxt_r         : t_reg;
 
-  . -- Memoryless signals in p_comb (wires used as local auxiliary variables)
-    SIGNAL s             : t_comb;
+  . -- Memoryless signals and auxiliary variables in p_comb
+    -- . For unique representation of variables in p_comb as signal wires, the p_comb
+    --   should assign each field in t_comb only once to a variable. It is allowed to
+    --   reasign a t_comb variable in p_comb, so use it as a temporary auxiliary
+    --   variable, but then only the last assignment value will be visible via the
+    --   signal dbg_wires in the Wave window.
+    SIGNAL dbg_wires     : t_comb;
 
-  . -- Structural signals (wires used to connect components and IO)
+  . -- Structural signals (wires used to connect r, nxt_r to other components and to
+    -- the entity IO)
 
   . -- Pipeline registers
     SIGNAL in_data_p     : ...
@@ -135,8 +141,9 @@ Implementation steps:
       -- State variable
       VARIABLE v : t_reg;
       -- Auxiliary variables
-      VARIABLE v_*   -- optional, use to improve code readability
-                     -- use v. only on left side? use separate v_* to clearly indicate when we use it also on the right side of assignments ?
+      --VARIABLE v_*   -- optional, use to improve code readability
+      --               -- use v. only on left side? use separate v_* to clearly indicate when we use it also on the right side of assignments ?
+      VARIABLE w : t_comb;
     BEGIN
       v := r;      -- default keep existing state
       v.* := ...;  -- default force specific values, e.g. set strobes to '0',
@@ -152,7 +159,7 @@ Implementation steps:
       nxt_r <= v;
 
       -- memory less signals, only for view in wave window
-      s <= d;
+      dbg_wires <= w;
     END PROCESS;
 
   . -- Pipelining