Merge branch 'RTSD-209' into 'master'

Porting ddio/iobuf for Intel Agilex 7

Closes RTSD-209

See merge request !364

libraries/technology/iobuf/hdllib.cfg

 hdl_lib_name = tech_iobuf
 hdl_library_clause_name = tech_iobuf_lib
-hdl_lib_uses_synth = technology ip_stratixiv_ddio ip_arria10_ddio ip_arria10_e3sge3_ddio ip_arria10_e1sg_ddio ip_arria10_e2sg_ddio
+hdl_lib_uses_synth = technology ip_stratixiv_ddio ip_arria10_ddio ip_arria10_e3sge3_ddio ip_arria10_e1sg_ddio ip_arria10_e2sg_ddio ip_agi027_xxxx_ddio
 hdl_lib_uses_sim = 
 hdl_lib_technology = 
 hdl_lib_disclose_library_clause_names =
@@ -9,6 +9,7 @@ hdl_lib_disclose_library_clause_names =
     ip_arria10_e3sge3_ddio  ip_arria10_e3sge3_ddio_lib
     ip_arria10_e1sg_ddio    ip_arria10_e1sg_ddio_lib
     ip_arria10_e2sg_ddio    ip_arria10_e2sg_ddio_lib
+    ip_agi027_xxxx_ddio     ip_agi027_xxxx_ddio_lib
 
 synth_files =
     tech_iobuf_component_pkg.vhd

libraries/technology/iobuf/tech_iobuf_component_pkg.vhd

 -- -----------------------------------------------------------------------------
 --
--- Copyright (C) 2014
+-- Copyright 2014-2023
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
 --
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
 --
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
 --
 -- -----------------------------------------------------------------------------
-
--- Purpose: IP components declarations for various devices that get wrapped by the tech components
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
+-- Purpose: 
+--   IP components declarations for various devices that get wrapped by the tech components
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -187,4 +189,36 @@ package tech_iobuf_component_pkg is
   );
   end component;
 
+  -----------------------------------------------------------------------------
+  -- ip_agi027_xxxx
+  -----------------------------------------------------------------------------
+
+  component ip_agi027_xxxx_ddio_in is
+  generic (
+    g_width : natural := 1
+  );
+  port (
+    in_dat      : in  std_logic_vector(g_width - 1 downto 0);
+    in_clk      : in  std_logic;
+    in_clk_en   : in  std_logic := '1';  -- Not Connected
+    rst         : in  std_logic := '0';
+    out_dat_hi  : out std_logic_vector(g_width - 1 downto 0);
+    out_dat_lo  : out std_logic_vector(g_width - 1 downto 0)
+  );
+  end component;
+
+  component ip_agi027_xxxx_ddio_out is
+  generic(
+    g_width : natural := 1
+  );
+  port (
+    rst        : in   std_logic := '0';
+    in_clk     : in   std_logic;
+    in_clk_en  : in   std_logic := '1';  -- Not Connected
+    in_dat_hi  : in   std_logic_vector(g_width - 1 downto 0);
+    in_dat_lo  : in   std_logic_vector(g_width - 1 downto 0);
+    out_dat    : out  std_logic_vector(g_width - 1 downto 0)
+  );
+  end component;
+
 end tech_iobuf_component_pkg;

libraries/technology/iobuf/tech_iobuf_ddio_in.vhd

 -- -----------------------------------------------------------------------------
 --
--- Copyright (C) 2014
+-- Copyright 2014-2023
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
 --
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
 --
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
 --
 -- -----------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
 
 library ieee, technology_lib;
 use ieee.std_logic_1164.all;
@@ -31,6 +33,7 @@ library ip_arria10_ddio_lib;
 library ip_arria10_e3sge3_ddio_lib;
 library ip_arria10_e1sg_ddio_lib;
 library ip_arria10_e2sg_ddio_lib;
+library ip_agi027_xxxx_ddio_lib;
 
 entity tech_iobuf_ddio_in is
   generic (
@@ -79,4 +82,10 @@ begin
     port map (in_dat, in_clk, in_clk_en, rst, out_dat_hi, out_dat_lo);
   end generate;
 
+  gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
+    u0 : ip_agi027_xxxx_ddio_in
+    generic map (g_width)
+    port map (in_dat, in_clk, in_clk_en, rst, out_dat_hi, out_dat_lo);
+  end generate;
+
 end architecture;

libraries/technology/iobuf/tech_iobuf_ddio_out.vhd

 -- -----------------------------------------------------------------------------
 --
--- Copyright (C) 2014
+-- Copyright 2014-2023
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
 --
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
 --
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
 --
 -- -----------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
 
 library ieee, technology_lib;
 use ieee.std_logic_1164.all;
@@ -31,6 +33,7 @@ library ip_arria10_ddio_lib;
 library ip_arria10_e3sge3_ddio_lib;
 library ip_arria10_e1sg_ddio_lib;
 library ip_arria10_e2sg_ddio_lib;
+library ip_agi027_xxxx_ddio_lib;
 
 entity tech_iobuf_ddio_out is
   generic (
@@ -79,4 +82,10 @@ begin
     port map (rst, in_clk, in_clk_en, in_dat_hi, in_dat_lo, out_dat);
   end generate;
 
+  gen_ip_agi027_xxxx : if g_technology = c_tech_agi027_xxxx generate
+    u0 : ip_agi027_xxxx_ddio_out
+    generic map (g_width)
+    port map (rst, in_clk, in_clk_en, in_dat_hi, in_dat_lo, out_dat);
+  end generate;
+
 end architecture;

libraries/technology/ip_agi027_xxxx/ddio/README.txt

+README.txt for $HDL_WORK/libraries/technology/ip_agi027_xxxx/ddio
+
+Contents:
+
+1) DDIO components
+2) Agilex7 IP
+3) Synthesis trials
+4) Issues
+
+
+1) DDIO components:
+
+  ip_agi027_xxxx_ddio_in.vhd   = Double Date Rate input
+  ip_agi027_xxxx_ddio_out.vhd  = Double Date Rate output
+  
+
+2) Agilex7 IP
+
+  In the past, the components altddio_in and altddio_out were used by the StratixIV IP. For more information about this see the
+  README.txt from ip_arria10_e2sg/ddio. Quartus convert them using the altera_gpio component for Arria10.
+  
+  The altera_gpio component is not part of the default Quartus tool libraries, but instead it is created by Qsys together
+  with the IP. This makes that the altera_gpio can not easily be used in simulation and synthesis like was possible with altera_mf
+  in for Stratix IV (Quartus 11.1). 
+  
+  The ddio_in component is used by the PPSH and the ddio_out component is used by the ADUH. In both cases the g_width=1.
+  The Agilex7 IP can be generated using a fixed width of 1. Therefore the same parameter settings are used (the width was set to 1)
+  in the conversion from Quartus v19.4 for arria10_e2sg to Quartus 23.2 for agi027_xxxxs and these IP source files are stored as:
+  
+    ip_agi027_xxxx_ddio_in_1.ip
+    ip_agi027_xxxx_ddio_out_1.ip
+  
+  If the application would need a wider port then it can achieve this by instantiating the IP multiple times. This approach
+  avoids having to generate DDIO IP for every possible width. An alternative would be:
+  - to generate IP for e.g. width=16 and assuming that that is sufficient for all applications. Any application that uses less
+    width then leaves these IO unconnected so that the unused IO will get optimized away by synthesis.
+  - create the IP when it is needed, this scheme is more difficult to manage but is something to consider for the future.
+
+  The IP needs to be generated using:
+  
+   generate_ip_libs iwave
+  
+  to create the simulation and synthesis files, because these are initially not kept in the git repository, only the IP source files.
+ 
+ 
+3) Synthesis trials
+
+  No synthesis trials have taken place for the Agilex 7. When it is preferable to verify that the DDIO IP actually synthesise to the
+  appropriate FPGA resources, use the Quartus project quartus/ddio.qsf from the ip_arria10/ram/ folder and follow the steps in the the
+  README.txt from the ip_agi027_xxxx/fifo or */ram folder. Use the Quartus GUI to manually select a top level component for synthesis
+  e.g. by right clicking the entity vhd file in the file tab of the Quartus project navigator window.
+  Then check the resource usage in the synthesis and fitter reports.
+
+
+4) Issues
+
+a) Simulation model does not work (for Quartus 14.1, not tried for Quartus 15.0 and Quartus 23.2)
+
+  The simulation model for the DDIO does not compile ok because a din port is missing in the ddio_out and a dout port is
+  missing in the ddio_in. Adding this ports manualy does work for compile, but when the component is loaded as a simulation
+  then Modelsim reports some internal error on the IP. The compile also does not work when using 'do msim_setup.tcl', so
+  there is something wrong with the DDIO simulation model. The synthesis of the DDIO IP using ddio.qpf does work.
+  
+  The work around is not not use the simulation model, but instead use a behavioral simulation model for the IP:
+     sim/ip_agi027_xxxx_ddio_in_1.vhd
+     sim/ip_agi027_xxxx_ddio_out_1.vhd
+     sim/tb_ip_agi027_xxxx_ddio_1.vhd   = self checking tb for ip_agi027_xxxx_ddio_in_1 -> ip_agi027_xxxx_ddio_out_1
+  
+  The selection between the IP model or the behavioral model is made in the compile_ip.tcl script.

libraries/technology/ip_agi027_xxxx/ddio/compile_ip.tcl

+# ------------------------------------------------------------------------------
+#
+# Copyright 2023
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# ------------------------------------------------------------------------------
+#
+# Author: D.F. Brouwer
+# Description:
+#   This file is based on generated file mentor/msim_setup.tcl.
+#   - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+#   - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+#   - replace QSYS_SIMDIR by IP_DIR
+#   - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist
+
+set IPMODEL "SIM";
+#set IPMODEL "PHY";
+
+if {$IPMODEL=="PHY"} { 
+    # OUTDATED AND NOT USED!!
+    # This file is based on Qsys-generated file msim_setup.tcl.
+    set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_ddio_in_1/sim"
+        
+    #vlib ./work/         ;# Assume library work already exists
+    vmap ip_agi027_xxxx_ddio_in_1_altera_gpio_core10_2100  ./work/
+    vmap ip_agi027_xxxx_ddio_in_1_altera_gpio_2100         ./work/
+    
+    vlog -sv "$IP_DIR/../altera_gpio_core10_2100/sim/mentor/altera_gpio.sv"                       -work ip_agi027_xxxx_ddio_in_1_altera_gpio_core10_2100
+    
+    vcom     "$IP_DIR/../altera_gpio_2100/sim/ip_agi027_xxxx_ddio_in_1_altera_gpio_2100_nhqe4ta.vhd"  -work ip_agi027_xxxx_ddio_in_1_altera_gpio_2100
+    vcom     "$IP_DIR/ip_agi027_xxxx_ddio_in_1.vhd"
+
+
+    set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_ddio_out_1/sim"
+
+    #vlib ./work/         ;# Assume library work already exists
+    vmap ip_agi027_xxxx_ddio_out_1_altera_gpio_core10_2100 ./work/
+    vmap ip_agi027_xxxx_ddio_out_1_altera_gpio_2100        ./work/    
+    
+    vlog -sv "$IP_DIR/../altera_gpio_core10_2100/sim/mentor/altera_gpio.sv"                       -work ip_agi027_xxxx_ddio_out_1_altera_gpio_core10_2100
+    
+    vcom     "$IP_DIR/../altera_gpio_2100/sim/ip_agi027_xxxx_ddio_out_1_altera_gpio_2100_e4tgwdq.vhd" -work ip_agi027_xxxx_ddio_out_1_altera_gpio_2100
+    vcom     "$IP_DIR/ip_agi027_xxxx_ddio_out_1.vhd"
+
+} else {
+
+    # This file uses a behavioral model because the PHY model does not compile OK, see README.txt.
+    set SIM_DIR "$env(HDL_WORK)/libraries/technology/ip_agi027_xxxx/ddio/sim/"
+    
+    vcom "$SIM_DIR/ip_agi027_xxxx_ddio_in_1.vhd"
+    vcom "$SIM_DIR/ip_agi027_xxxx_ddio_out_1.vhd"
+    vcom "$SIM_DIR/tb_ip_agi027_xxxx_ddio_1.vhd"
+    
+}

libraries/technology/ip_agi027_xxxx/ddio/hdllib.cfg

+hdl_lib_name = ip_agi027_xxxx_ddio
+hdl_library_clause_name = ip_agi027_xxxx_ddio_lib
+hdl_lib_uses_synth = technology
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_agi027_xxxx
+
+synth_files =
+    ip_agi027_xxxx_ddio_in.vhd
+    ip_agi027_xxxx_ddio_out.vhd
+    
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    $HDL_WORK/libraries/technology/ip_agi027_xxxx/ddio/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_agi027_xxxx_ddio_in_1/ip_agi027_xxxx_ddio_in_1.qip
+    $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_agi027_xxxx_ddio_out_1/ip_agi027_xxxx_ddio_out_1.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_agi027_xxxx_ddio_in_1.ip
+    ip_agi027_xxxx_ddio_out_1.ip

libraries/technology/ip_agi027_xxxx/ddio/ip_agi027_xxxx_ddio_in.vhd

+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author: 
+--   D.F. Brouwer
+-- Purpose:
+--   RadioHDL wrapper for ip_agi027_xxxx_ddio_in_1 to support g_width >= 1
+-- Reference:
+--   Copied component declaration and instance example from
+--   ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_in.vhd and verified them against
+--   generated/altera_gpio_2100/sim/ip_agi027_xxxx_ddio_in_1_altera_gpio_2100_nhqe4ta
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ip_agi027_xxxx_ddio_in is
+  generic (
+    g_width : natural := 1
+  );
+  port (
+    in_dat      : in  std_logic_vector(g_width - 1 downto 0);
+    in_clk      : in  std_logic;
+    in_clk_en   : in  std_logic := '1';  -- Not Connected
+    rst         : in  std_logic := '0';
+    out_dat_hi  : out std_logic_vector(g_width - 1 downto 0);
+    out_dat_lo  : out std_logic_vector(g_width - 1 downto 0)
+  );
+end ip_agi027_xxxx_ddio_in;
+
+architecture str of ip_agi027_xxxx_ddio_in is
+  component ip_agi027_xxxx_ddio_in_1 is
+        port (
+                datain    : in  std_logic_vector(0 downto 0) := (others => '0');  -- pad_in.export
+                ck        : in  std_logic                    := '0';  -- ck.export
+                aclr      : in  std_logic                    := '0';  -- aclr.export
+                dataout_h : out std_logic_vector(0 downto 0);  -- dataout_h.fragment
+                dataout_l : out std_logic_vector(0 downto 0)  -- dataout_l.fragment
+        );
+  end component;
+begin
+  gen_w : for I in g_width - 1 downto 0 generate
+    u_ip_agi027_xxxx_ddio_in_1 : ip_agi027_xxxx_ddio_in_1
+    port map (
+      datain    => in_dat(I downto I),
+      ck        => in_clk,
+      aclr      => rst,
+      dataout_h => out_dat_hi(I downto I),
+      dataout_l => out_dat_lo(I downto I)
+    );
+  end generate;
+
+end str;

libraries/technology/ip_agi027_xxxx/ddio/ip_agi027_xxxx_ddio_out.vhd

+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author: 
+--   D.F. Brouwer
+-- Purpose:
+--   RadioHDL wrapper for ip_agi027_xxxx_ddio_out_1 to support g_width >= 1
+-- Reference:
+--   Copied component declaration and instance example from
+--   ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_out.vhd and verified them against
+--   generated/altera_gpio_2100/sim/ip_agi027_xxxx_ddio_out_1_altera_gpio_2100_e4tgwdq
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ip_agi027_xxxx_ddio_out is
+  generic(
+    g_width : natural := 1
+  );
+  port (
+    rst        : in   std_logic := '0';
+    in_clk     : in   std_logic;
+    in_clk_en  : in   std_logic := '1';  -- Not Connected
+    in_dat_hi  : in   std_logic_vector(g_width - 1 downto 0);
+    in_dat_lo  : in   std_logic_vector(g_width - 1 downto 0);
+    out_dat    : out  std_logic_vector(g_width - 1 downto 0)
+  );
+end ip_agi027_xxxx_ddio_out;
+
+architecture str of ip_agi027_xxxx_ddio_out is
+  component ip_agi027_xxxx_ddio_out_1 is
+        port (
+                dataout  : out std_logic_vector(0 downto 0);  -- pad_out.export
+                outclock : in  std_logic                    := '0';  -- ck.export
+                aclr     : in  std_logic                    := '0';  -- aclr.export
+                datain_h : in  std_logic_vector(0 downto 0) := (others => '0');  -- datain_h.fragment
+                datain_l : in  std_logic_vector(0 downto 0) := (others => '0')  -- datain_l.fragment
+        );
+  end component;
+begin
+  gen_w : for I in g_width - 1 downto 0 generate
+    u_ip_agi027_xxxx_ddio_out_1 : ip_agi027_xxxx_ddio_out_1
+    port map (
+      dataout  => out_dat(I downto I),
+      outclock => in_clk,
+      aclr     => rst,
+      datain_h => in_dat_hi(I downto I),
+      datain_l => in_dat_lo(I downto I)
+    );
+  end generate;
+
+end str;

libraries/technology/ip_agi027_xxxx/ddio/sim/ip_agi027_xxxx_ddio_in_1.vhd

+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author: 
+--   D.F. Brouwer
+-- Purpose:
+--   Simulation model for DDIO in
+-- Description:
+--   The double data rate datain samples that arrive at time series t0, t1, t2,
+--   ... get output with samples t0, t2, ... in dataout_l and samples t1, t3,
+--   ... in dataout_h. Hence dataout = dataout_h & dataout_l contains the
+--   time series samples in little endian format with the first sample in the
+--   LSpart as shown in the timing diagram:
+--               _   _   _   _
+--     ck       | |_| |_| |_| |_
+--     datain    0 1 2 3 4 5 6 7
+--     in_dat_r      1   3   5
+--     in_dat_f    0   2   4
+--     dataout_h     1   3   5
+--     dataout_l     0   2   4
+-- Reference:
+--   Copied from ip_arria10_e2sg/ddio/sim/ip_arria10_e2sg_ddio_in_1.vhd 
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity ip_agi027_xxxx_ddio_in_1 is
+	port (
+		datain    : in  std_logic_vector(0 downto 0) := (others => '0');
+		ck        : in  std_logic                    := '0';
+		aclr      : in  std_logic                    := '0';
+		dataout_h : out std_logic_vector(0 downto 0);
+		dataout_l : out std_logic_vector(0 downto 0)
+	);
+end ip_agi027_xxxx_ddio_in_1;
+
+architecture beh of ip_agi027_xxxx_ddio_in_1 is
+  signal in_dat_r   : std_logic;
+  signal in_dat_f   : std_logic;
+begin
+  in_dat_r <= datain(0) when rising_edge(ck);
+  in_dat_f <= datain(0) when falling_edge(ck);
+
+  dataout_h <= (others => in_dat_r);
+  dataout_l <= (others => in_dat_f) when rising_edge(ck);
+end beh;

libraries/technology/ip_agi027_xxxx/ddio/sim/ip_agi027_xxxx_ddio_out_1.vhd

+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author: 
+--   D.F. Brouwer
+-- Purpose:
+--   Simulation model for DDIO out
+-- Description:
+--   This function is the inverse of DDIO in as described in ip_agi027_xxxx_ddio_in_1.
+--   The timing diagram:
+--                 _   _   _   _   _
+--     outclock   | |_| |_| |_| |_| |_
+--     datain_h        1   3   5
+--     datain_l        0   2   4
+--     dataout @ r         1   3   5
+--     dataout @ f       0   2   4
+--     dataout           0 1 2 3 4 5 6 7
+-- Reference:
+--   Copied from ip_arria10_e2sg/ddio/sim/ip_arria10_e2sg_ddio_out_1.vhd 
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity ip_agi027_xxxx_ddio_out_1 is
+	port (
+		dataout  : out std_logic_vector(0 downto 0);
+		outclock : in  std_logic                    := '0';
+		aclr     : in  std_logic                    := '0';
+		datain_h : in  std_logic_vector(0 downto 0) := (others => '0');
+		datain_l : in  std_logic_vector(0 downto 0) := (others => '0')
+	);
+end ip_agi027_xxxx_ddio_out_1;
+
+architecture beh of ip_agi027_xxxx_ddio_out_1 is
+  signal out_dat_r   : std_logic;
+  signal out_dat_f   : std_logic;
+begin
+  dataout <= datain_l when falling_edge(outclock) else
+             datain_h when rising_edge(outclock);
+end beh;

libraries/technology/ip_agi027_xxxx/ddio/sim/tb_ip_agi027_xxxx_ddio_1.vhd

+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author: 
+--   D.F. Brouwer
+-- Purpose:
+--   Test bench for the DDIO in and out simulation models
+-- Description:
+--   The timing diagram:
+--               _   _   _   _
+--     inclock  | |_| |_| |_| |_
+--     datain    0 1 2 3 4 5 6 7
+--     data_h        1   3   5
+--     data_l        0   2   4
+--     dataout         0 1 2 3 4 5 6 7
+--
+-- Usage:
+--   The tb is self checking (p_verify) and self stopping (tb_end)
+--
+--   . Load the simulation by right mouse selecting the entity in library work
+--   > as 3
+--   > run -a
+-- Reference:
+--   Copied from ip_arria10_e2sg/ddio/sim/tb_ip_arria10_e2sg_ddio_1.vhd 
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity tb_ip_agi027_xxxx_ddio_1 is
+end tb_ip_agi027_xxxx_ddio_1;
+
+architecture tb of tb_ip_agi027_xxxx_ddio_1 is
+  constant c_clk_period : time := 10 ns;
+
+  signal tb_end      : std_logic := '0';
+  signal clk         : std_logic := '1';
+  signal in_dat      : std_logic;
+  signal in_data     : std_logic_vector(0 downto 0);
+  signal data_h      : std_logic_vector(0 downto 0);
+  signal data_l      : std_logic_vector(0 downto 0);
+  signal out_data    : std_logic_vector(0 downto 0);
+  signal out_dat     : std_logic;
+  signal out_dat_exp : std_logic;
+begin
+  tb_end <= '0', '1' after 100 * c_clk_period;
+
+  clk <= not clk or tb_end after c_clk_period / 2;
+
+  p_in : process
+  begin
+    -- 0
+    in_dat <= '0';
+    wait until falling_edge(clk);
+    in_dat <= '0';
+    wait until rising_edge(clk);
+    -- 1
+    in_dat <= '0';
+    wait until falling_edge(clk);
+    in_dat <= '1';
+    wait until rising_edge(clk);
+    -- 2
+    in_dat <= '1';
+    wait until falling_edge(clk);
+    in_dat <= '0';
+    wait until rising_edge(clk);
+    -- 3
+    in_dat <= '1';
+    wait until falling_edge(clk);
+    in_dat <= '1';
+    wait until rising_edge(clk);
+    -- 2
+    in_dat <= '1';
+    wait until falling_edge(clk);
+    in_dat <= '0';
+    wait until rising_edge(clk);
+  end process;
+
+  in_data(0) <= in_dat;
+
+  u_ddio_in : entity work.ip_agi027_xxxx_ddio_in_1
+	port map (
+		datain    => in_data,
+		ck        => clk,
+		dataout_h => data_h,
+		dataout_l => data_l
+	);
+
+  u_ddio_out : entity work.ip_agi027_xxxx_ddio_out_1
+	port map (
+		dataout  => out_data,
+		outclock => clk,
+		datain_h => data_h,
+		datain_l => data_l
+	);
+
+	out_dat <= out_data(0);
+
+	out_dat_exp <= transport in_dat after c_clk_period * 1.5 + 1 ps;
+
+	p_verify : process(clk)
+	begin
+	  if falling_edge(clk) then
+	    assert out_dat = out_dat_exp report "tb_ip_agi027_xxxx_ddio_1: Error, unexpeced data at falling edge";
+	  end if;
+	  if rising_edge(clk) then
+	    assert out_dat = out_dat_exp report "tb_ip_agi027_xxxx_ddio_1: Error, unexpeced data at rising edge";
+	  end if;
+	end process;
+end tb;