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Commit fe69b4f0 authored by Eric Kooistra's avatar Eric Kooistra
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Added func_tech_ddr_module_size() to determine the module memory size in GBytes.

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...@@ -37,7 +37,7 @@ PACKAGE tech_ddr_pkg IS ...@@ -37,7 +37,7 @@ PACKAGE tech_ddr_pkg IS
a_col_w : NATURAL; -- = 10 <= a_w, col address width, via a_w lines a_col_w : NATURAL; -- = 10 <= a_w, col address width, via a_w lines
ba_w : NATURAL; -- = 3 ba_w : NATURAL; -- = 3
dq_w : NATURAL; -- = 64 dq_w : NATURAL; -- = 64
dqs_w : NATURAL; -- = 8 = dq_w / nof_dq_per_dqs; dqs_w : NATURAL; -- = 8 = dq_w / nof_dq_per_dqs
dm_w : NATURAL; -- = 8 dm_w : NATURAL; -- = 8
cs_w : NATURAL; -- = 2 cs_w : NATURAL; -- = 2
clk_w : NATURAL; -- = 2 clk_w : NATURAL; -- = 2
...@@ -56,6 +56,8 @@ PACKAGE tech_ddr_pkg IS ...@@ -56,6 +56,8 @@ PACKAGE tech_ddr_pkg IS
CONSTANT c_tech_ddr_4g_800m : t_c_tech_ddr := ( 800, TRUE, 15, 15, 10, 3, 64, 8, 8, 2, 2, 14, 4, 2, 32, 256, 64, 7); CONSTANT c_tech_ddr_4g_800m : t_c_tech_ddr := ( 800, TRUE, 15, 15, 10, 3, 64, 8, 8, 2, 2, 14, 4, 2, 32, 256, 64, 7);
CONSTANT c_tech_ddr_4g_800m_slave : t_c_tech_ddr := ( 800, FALSE, 15, 15, 10, 3, 64, 8, 8, 2, 2, 14, 4, 2, 32, 256, 64, 7); CONSTANT c_tech_ddr_4g_800m_slave : t_c_tech_ddr := ( 800, FALSE, 15, 15, 10, 3, 64, 8, 8, 2, 2, 14, 4, 2, 32, 256, 64, 7);
FUNCTION func_tech_ddr_module_size(c_ddr : t_c_tech_ddr) RETURN NATURAL; -- return DDR module size in GByte
-- PHY in, inout and out signal records -- PHY in, inout and out signal records
TYPE t_tech_ddr_phy_in IS RECORD TYPE t_tech_ddr_phy_in IS RECORD
evt : STD_LOGIC; -- event signal is Not Connected to DDR3 PHY evt : STD_LOGIC; -- event signal is Not Connected to DDR3 PHY
...@@ -134,5 +136,16 @@ PACKAGE tech_ddr_pkg IS ...@@ -134,5 +136,16 @@ PACKAGE tech_ddr_pkg IS
END tech_ddr_pkg; END tech_ddr_pkg;
PACKAGE BODY tech_ddr_pkg IS PACKAGE BODY tech_ddr_pkg IS
FUNCTION func_tech_ddr_module_size(c_ddr : t_c_tech_ddr) RETURN NATURAL IS
CONSTANT c_chip_addr_w : NATURAL := ceil_log2(c_ddr.cs_w); -- Chip sel lines converted to logical address
CONSTANT c_dq_address_w : NATURAL := c_chip_addr_w + c_ddr.ba_w + c_ddr.a_w + c_ddr.a_col_w;
CONSTANT c_dq_nof_bytes_w : NATURAL := 8; -- both dw_q = 64 and 72 are regarded as having 8 bytes (either with 8 or 9 bits per byte)
CONSTANT c_module_nof_bytes_w : NATURAL := c_dq_address_w + c_dq_nof_bytes_w;
CONSTANT c_1GB_w : NATURAL := 30;
BEGIN
RETURN 2**(c_module_nof_bytes_w-c_1GB_w);
END;
END tech_ddr_pkg; END tech_ddr_pkg;
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