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Commit fdc93de7 authored by Pieter Donker's avatar Pieter Donker
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L2SDP-200: backup

parent 70a06fd9
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2 merge requests!100Removed text for XSub that is now written in Confluence Subband correlator...,!67Resolve L2SDP-200
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applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
+ 38
− 46
View file @ fdc93de7
...@@ -64,7 +64,7 @@ USE work.sdp_pkg.ALL; ...@@ -64,7 +64,7 @@ USE work.sdp_pkg.ALL;
ENTITY sdp_statistics_offload IS ENTITY sdp_statistics_offload IS
GENERIC ( GENERIC (
g_statistics_type : STRING := "SST"; g_statistics_type : STRING := "SST";
g_offload_time : NATURAL := 0; g_offload_time : NATURAL := 0; -- from wave window (330320nS - 83105nS) / 50nS = 12361 cycles.
g_beamset_id : NATURAL := 0 g_beamset_id : NATURAL := 0
); );
PORT ( PORT (
...@@ -76,8 +76,8 @@ ENTITY sdp_statistics_offload IS ...@@ -76,8 +76,8 @@ ENTITY sdp_statistics_offload IS
dp_rst : IN STD_LOGIC; dp_rst : IN STD_LOGIC;
-- from MM master multiplexer -- from MM master multiplexer
master_mosi : IN t_mem_mosi := c_mem_mosi_rst; master_mosi : OUT t_mem_mosi; -- := c_mem_mosi_rst;
master_miso : OUT t_mem_miso; master_miso : IN t_mem_miso;
reg_enable_mosi : IN t_mem_mosi := c_mem_mosi_rst; reg_enable_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_enable_miso : OUT t_mem_miso; reg_enable_miso : OUT t_mem_miso;
...@@ -103,17 +103,16 @@ END sdp_statistics_offload; ...@@ -103,17 +103,16 @@ END sdp_statistics_offload;
ARCHITECTURE str OF sdp_statistics_offload IS ARCHITECTURE str OF sdp_statistics_offload IS
CONSTANT c_version : NATURAL := 1; CONSTANT c_version : NATURAL := 1;
CONSTANT c_marker : NATURAL := sel_a_b((g_statistics_type="BST"), 66, sel_a_b((g_statistics_type="XST"), 88, 83)); -- based on g_statistics_type: 'S'=0x53="SST", 'B'=0x42="BST", 'X'=0x58="XST" CONSTANT c_marker : NATURAL := sel_a_b((g_statistics_type="BST"), 66, sel_a_b((g_statistics_type="XST"), 88, 83)); -- based on g_statistics_type: 'S'=0x53="SST", 'B'=0x42="BST", 'X'=0x58="XST"
CONSTANT c_nof_statistics_per_packet : NATURAL := 0; CONSTANT c_nof_statistics_per_packet : NATURAL := 0;
CONSTANT c_data_size : NATURAL := 2; CONSTANT c_data_size : NATURAL := 2;
CONSTANT c_step_size : NATURAL := 4; CONSTANT c_step_size : NATURAL := 4;
CONSTANT c_nof_data : NATURAL := 512; CONSTANT c_nof_data : NATURAL := 512;
CONSTANT c_block_size : NATURAL := c_nof_data * c_data_size * (c_step_size / c_data_size); CONSTANT c_block_size : NATURAL := c_nof_data * c_data_size * (c_step_size / c_data_size);
CONSTANT c_nof_streams : NATURAL := 1; CONSTANT c_nof_streams : NATURAL := 1;
CONSTANT c_nof_signal_inputs : NATURAL := sel_a_b(g_statistics_type="BST", 0, sel_a_b(g_statistics_type="XST", c_sdp_S_pn, 1)); CONSTANT c_nof_signal_inputs : NATURAL := sel_a_b(g_statistics_type="BST", 0, sel_a_b(g_statistics_type="XST", c_sdp_S_pn, 1));
CONSTANT c_nof_statistics_per_package : NATURAL := sel_a_b(g_statistics_type="BST", c_sdp_S_sub_bf, sel_a_b(g_statistics_type="XST", (c_sdp_S_pn*c_sdp_S_pn*c_nof_complex), c_sdp_N_sub)); CONSTANT c_nof_statistics_per_package : NATURAL := sel_a_b(g_statistics_type="BST", c_sdp_S_sub_bf, sel_a_b(g_statistics_type="XST", (c_sdp_S_pn*c_sdp_S_pn*c_nof_complex), c_sdp_N_sub));
CONSTANT c_beamlet_id : NATURAL := g_beamset_id * c_sdp_S_sub_bf; CONSTANT c_beamlet_id : NATURAL := g_beamset_id * c_sdp_S_sub_bf;
TYPE t_reg IS RECORD TYPE t_reg IS RECORD
...@@ -122,16 +121,14 @@ ARCHITECTURE str OF sdp_statistics_offload IS ...@@ -122,16 +121,14 @@ ARCHITECTURE str OF sdp_statistics_offload IS
start_pulse : STD_LOGIC; start_pulse : STD_LOGIC;
dp_header_info : STD_LOGIC_VECTOR(1023 DOWNTO 0); dp_header_info : STD_LOGIC_VECTOR(1023 DOWNTO 0);
data_id : STD_LOGIC_VECTOR(31 DOWNTO 0); data_id : STD_LOGIC_VECTOR(31 DOWNTO 0);
last_mm_done : STD_LOGIC;
END RECORD; END RECORD;
CONSTANT c_reg_rst : t_reg := (0, 0, '0', (OTHERS => '0'), (OTHERS => '0')); CONSTANT c_reg_rst : t_reg := (0, 0, '0', (OTHERS => '0'), (OTHERS => '0'), '0');
SIGNAL r : t_reg; SIGNAL r : t_reg;
SIGNAL d : t_reg; SIGNAL d : t_reg;
SIGNAL m_mosi : t_mem_mosi;
SIGNAL m_miso : t_mem_miso;
SIGNAL trigger : STD_LOGIC := '0'; SIGNAL trigger : STD_LOGIC := '0';
SIGNAL nof_cycles_dly : NATURAL := 0; SIGNAL nof_cycles_dly : NATURAL := 0;
SIGNAL mm_done : STD_LOGIC := '0'; SIGNAL mm_done : STD_LOGIC := '0';
...@@ -150,9 +147,6 @@ ARCHITECTURE str OF sdp_statistics_offload IS ...@@ -150,9 +147,6 @@ ARCHITECTURE str OF sdp_statistics_offload IS
BEGIN BEGIN
m_mosi <= master_mosi;
master_miso <= m_miso;
-- count number of sop's in a sync interval -- count number of sop's in a sync interval
p_bsn_at_sync : PROCESS(in_sosi) p_bsn_at_sync : PROCESS(in_sosi)
BEGIN BEGIN
...@@ -190,12 +184,11 @@ BEGIN ...@@ -190,12 +184,11 @@ BEGIN
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Assemble offload info -- Assemble offload header info
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "eth_src_mac" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "eth_src_mac" )) <= eth_src_mac; dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "eth_src_mac" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "eth_src_mac" )) <= eth_src_mac;
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "udp_src_port") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "udp_src_port")) <= udp_src_port; dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "udp_src_port" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "udp_src_port" )) <= udp_src_port;
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "ip_src_addr" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "ip_src_addr" )) <= ip_src_addr; dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "ip_src_addr" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "ip_src_addr" )) <= ip_src_addr;
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_marker" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_marker" )) <= TO_UVEC(c_marker, 8); dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_marker" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_marker" )) <= TO_UVEC(c_marker, 8);
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_observation_id" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_observation_id" )) <= sdp_info.observation_id; dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_observation_id" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_observation_id" )) <= sdp_info.observation_id;
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_station_id" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_station_id" )) <= sdp_info.station_id; dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_station_id" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_station_id" )) <= sdp_info.station_id;
...@@ -214,11 +207,9 @@ BEGIN ...@@ -214,11 +207,9 @@ BEGIN
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_nof_signal_inputs" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_nof_signal_inputs" )) <= TO_UVEC(c_nof_signal_inputs, 8); dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_nof_signal_inputs" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_nof_signal_inputs" )) <= TO_UVEC(c_nof_signal_inputs, 8);
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_nof_statistics_per_package" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_nof_statistics_per_package" )) <= TO_UVEC(c_nof_statistics_per_package, 16); dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_nof_statistics_per_package" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_nof_statistics_per_package" )) <= TO_UVEC(c_nof_statistics_per_package, 16);
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_block_period" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_block_period" )) <= sdp_info.block_period; dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_block_period" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_block_period" )) <= sdp_info.block_period;
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "dp_bsn" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "dp_bsn" )) <= bsn_at_sync; dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "dp_bsn" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "dp_bsn" )) <= bsn_at_sync;
nof_cycles_dly <= gn_index * g_offload_time; nof_cycles_dly <= gn_index * g_offload_time;
sdp_data_id <= r.data_id; sdp_data_id <= r.data_id;
...@@ -231,26 +222,29 @@ BEGIN ...@@ -231,26 +222,29 @@ BEGIN
END IF; END IF;
END PROCESS; END PROCESS;
p_control_packet_offload : PROCESS(r, trigger, mm_done) p_control_packet_offload : PROCESS(r, trigger, mm_done)
BEGIN BEGIN
d <= r; d <= r;
d.last_mm_done <= mm_done;
-- assign sdp_data_id for different statistic types -- assign sdp_data_id for different statistic types
IF g_statistics_type = "SST" THEN IF g_statistics_type = "SST" THEN
d.data_id <= x"000000" & TO_UVEC(r.block_count, 8); d.data_id <= x"000000" & TO_UVEC(r.block_count, 8);
ELSIF g_statistics_type = "BST" THEN ELSIF g_statistics_type = "BST" THEN
d.data_id <= x"0000" & TO_UVEC(c_beamlet_id, 24); d.data_id <= x"0000" & TO_UVEC(c_beamlet_id, 24);
ELSIF g_statistics_type = "XST" THEN ELSIF g_statistics_type = "XST" THEN
d.data_id <= x"00" & TO_UVEC(0, 8) & TO_UVEC(0, 8) & TO_UVEC(0, 8); -- TODO fill fill in right values. d.data_id <= x"00" & TO_UVEC(0, 8) & TO_UVEC(0, 8) & TO_UVEC(0, 8); -- TODO: fill in right values for XST.
ELSE ELSE
d.data_id <= x"00000000"; d.data_id <= x"00000000";
END IF; END IF;
IF trigger = '1' OR mm_done = '1' THEN IF trigger = '1' AND d.block_count = 0 THEN
d.start_pulse <= '1';
END IF;
IF mm_done = '1' AND r.last_mm_done = '0' THEN
d.block_count <= r.block_count + 1; d.block_count <= r.block_count + 1;
IF (r.block_count + 1) mod 2 = 0 THEN IF r.block_count mod 2 = 0 THEN
d.start_address <= d.block_count / 2 * c_block_size; d.start_address <= r.block_count / 2 * c_block_size;
ELSE ELSE
d.start_address <= r.start_address + c_data_size; d.start_address <= r.start_address + c_data_size;
END IF; END IF;
...@@ -261,7 +255,7 @@ BEGIN ...@@ -261,7 +255,7 @@ BEGIN
d.dp_header_info <= dp_header_info; d.dp_header_info <= dp_header_info;
END IF; END IF;
IF d.block_count >= c_sdp_S_pn THEN IF r.block_count >= c_sdp_S_pn THEN
d.block_count <= 0; d.block_count <= 0;
d.start_address <= 0; d.start_address <= 0;
END IF; END IF;
...@@ -270,9 +264,6 @@ BEGIN ...@@ -270,9 +264,6 @@ BEGIN
u_mms_common_variable_delay : ENTITY common_lib.mms_common_variable_delay u_mms_common_variable_delay : ENTITY common_lib.mms_common_variable_delay
GENERIC MAP (
g_max_delay => 4
)
PORT MAP ( PORT MAP (
mm_rst => mm_rst, mm_rst => mm_rst,
mm_clk => mm_clk, mm_clk => mm_clk,
...@@ -295,24 +286,25 @@ BEGIN ...@@ -295,24 +286,25 @@ BEGIN
g_nof_data => c_nof_data g_nof_data => c_nof_data
) )
PORT MAP( PORT MAP(
rst => mm_rst, rst => dp_rst,
clk => mm_clk, clk => dp_clk,
start_pulse => r.start_pulse, start_pulse => r.start_pulse,
start_address => r.start_address, start_address => r.start_address,
mm_done => mm_done, mm_done => mm_done,
mm_mosi => m_mosi, mm_mosi => master_mosi,
mm_miso => m_miso, mm_miso => master_miso,
out_sosi => dp_block_from_mm_src_out, out_sosi => dp_block_from_mm_src_out,
out_siso => dp_block_from_mm_src_in out_siso => dp_block_from_mm_src_in
); );
u_dp_offload_tx_v3: ENTITY dp_lib.dp_offload_tx_v3 u_dp_offload_tx_v3: ENTITY dp_lib.dp_offload_tx_v3
GENERIC MAP ( GENERIC MAP (
g_nof_streams => c_nof_streams, g_nof_streams => c_nof_streams,
g_data_w => c_word_w, g_data_w => c_word_w,
g_symbol_w => c_byte_w, g_symbol_w => c_word_w,
g_hdr_field_arr => c_sdp_stat_hdr_field_arr, g_hdr_field_arr => c_sdp_stat_hdr_field_arr,
g_hdr_field_sel => c_sdp_stat_hdr_field_sel g_hdr_field_sel => c_sdp_stat_hdr_field_sel,
g_pipeline_ready => TRUE
) )
PORT MAP( PORT MAP(
mm_rst => mm_rst, mm_rst => mm_rst,
......
applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
+ 152
− 88
View file @ fdc93de7
...@@ -40,6 +40,7 @@ USE common_lib.common_mem_pkg.ALL; ...@@ -40,6 +40,7 @@ USE common_lib.common_mem_pkg.ALL;
USE common_lib.tb_common_pkg.ALL; USE common_lib.tb_common_pkg.ALL;
USE common_lib.tb_common_mem_pkg.ALL; USE common_lib.tb_common_mem_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL; USE common_lib.common_network_layers_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL; USE dp_lib.dp_stream_pkg.ALL;
USE work.sdp_pkg.ALL; USE work.sdp_pkg.ALL;
...@@ -47,7 +48,7 @@ USE work.sdp_pkg.ALL; ...@@ -47,7 +48,7 @@ USE work.sdp_pkg.ALL;
ENTITY tb_sdp_statistics_offload IS ENTITY tb_sdp_statistics_offload IS
GENERIC ( GENERIC (
g_statistics_type : STRING := "SST"; g_statistics_type : STRING := "SST";
g_nof_signal_inputs_per_pn : NATURAL := 4 g_nof_signal_inputs_per_pn : NATURAL := 12
); );
END tb_sdp_statistics_offload; END tb_sdp_statistics_offload;
...@@ -55,16 +56,20 @@ ARCHITECTURE tb OF tb_sdp_statistics_offload IS ...@@ -55,16 +56,20 @@ ARCHITECTURE tb OF tb_sdp_statistics_offload IS
CONSTANT c_dp_clk_period : TIME := 5 ns; -- 200 MHz CONSTANT c_dp_clk_period : TIME := 5 ns; -- 200 MHz
CONSTANT c_mm_clk_period : TIME := 20 ns; -- 50 MHz CONSTANT c_mm_clk_period : TIME := 20 ns; -- 50 MHz
CONSTANT c_cross_clock_domain_latency : NATURAL := 40; CONSTANT c_cross_clock_domain_latency : NATURAL := 20;
CONSTANT c_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0) := x"123456789ABC"; CONSTANT c_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0) := x"123456789ABC";
CONSTANT c_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0) := x"D001";
CONSTANT c_ip_src_addr : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0) := x"0A090807"; CONSTANT c_ip_src_addr : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0) := x"0A090807";
CONSTANT c_udp_src_port : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0) := x"D001";
-- used mm_adresses on mm bus -- used mm_adresses on mm bus "enable_mosi/miso"
CONSTANT c_mm_addr_enable : NATURAL := 0; CONSTANT c_mm_addr_enable : NATURAL := 0;
-- used mm_adresses on mm bus "hdr_dat_mosi/miso"
CONSTANT c_mm_addr_eth_src_mac : NATURAL := 1;
CONSTANT c_mm_addr_ip_src_addr : NATURAL := 13;
CONSTANT c_mm_addr_udp_src_port : NATURAL := 15;
-- used test ram size: c_block_size = c_nof_data * c_data_size * (c_step_size / c_data_size) => 512 * 2 * (4 / 2) = 2048 words per pair of signal inputs; -- used test ram size: c_nof_clk_per_block = c_nof_data * c_data_size * (c_step_size / c_data_size) => 512 * 2 * (4 / 2) = 2048 words per pair of signal inputs;
-- with 12 signal input, 6 pairs (blocks) we will fill 2 blocks for testing 2 * 2048 = 4096 = -- with 12 signal input, 6 pairs (blocks) we will fill 2 blocks for testing 2 * 2048 = 4096 =
CONSTANT c_nof_data : NATURAL := 512; CONSTANT c_nof_data : NATURAL := 512;
CONSTANT c_data_size : NATURAL := 2; CONSTANT c_data_size : NATURAL := 2;
...@@ -73,8 +78,10 @@ ARCHITECTURE tb OF tb_sdp_statistics_offload IS ...@@ -73,8 +78,10 @@ ARCHITECTURE tb OF tb_sdp_statistics_offload IS
CONSTANT c_ram_w : NATURAL := ceil_log2(c_ram_size); CONSTANT c_ram_w : NATURAL := ceil_log2(c_ram_size);
CONSTANT c_ram_buf : t_c_mem := (c_mem_ram_rd_latency, c_ram_w, 32, 2**c_ram_w, 'X'); CONSTANT c_ram_buf : t_c_mem := (c_mem_ram_rd_latency, c_ram_w, 32, 2**c_ram_w, 'X');
CONSTANT c_nof_block_per_sync : NATURAL := 20; -- sufficient to fit more than g_nof_signal_inputs_per_pn offload packets per sync interval
CONSTANT c_nof_clk_per_block : NATURAL := c_nof_data * c_data_size;
SIGNAL tb_end : STD_LOGIC := '0'; SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL tb_mm_reg_end : STD_LOGIC := '0';
SIGNAL dp_clk : STD_LOGIC := '1'; -- digital data path clock = 200 MHz (deser factor 4); SIGNAL dp_clk : STD_LOGIC := '1'; -- digital data path clock = 200 MHz (deser factor 4);
SIGNAL dp_rst : STD_LOGIC; SIGNAL dp_rst : STD_LOGIC;
...@@ -91,28 +98,39 @@ ARCHITECTURE tb OF tb_sdp_statistics_offload IS ...@@ -91,28 +98,39 @@ ARCHITECTURE tb OF tb_sdp_statistics_offload IS
SIGNAL hdr_dat_mosi : t_mem_mosi := c_mem_mosi_rst; SIGNAL hdr_dat_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL hdr_dat_miso : t_mem_miso; SIGNAL hdr_dat_miso : t_mem_miso;
SIGNAL offload_rx_hdr_dat_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL offload_rx_hdr_dat_miso : t_mem_miso;
SIGNAL in_sosi : t_dp_sosi := c_dp_sosi_rst; SIGNAL in_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL offload_sosi : t_dp_sosi; SIGNAL offload_sosi : t_dp_sosi;
SIGNAL offload_siso : t_dp_siso := c_dp_siso_rst; SIGNAL offload_siso : t_dp_siso := c_dp_siso_rst;
SIGNAL test_offload_sosi : t_dp_sosi; SIGNAL link_offload_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL link_offload_siso : t_dp_siso;
SIGNAL test_offload_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL test_offload_siso : t_dp_siso;
SIGNAL rx_hdr_fields_out : STD_LOGIC_VECTOR(1023 DOWNTO 0);
SIGNAL rx_hdr_fields_raw : STD_LOGIC_VECTOR(1023 DOWNTO 0) := (OTHERS => '0');
-- signals used to change settings of sdp_info -- signals used to change settings of sdp_info
SIGNAL gn_index : NATURAL := 15; SIGNAL gn_index : NATURAL := 1;
SIGNAL f_adc : STD_LOGIC := '0'; SIGNAL f_adc : STD_LOGIC := '0';
SIGNAL fsub_type : STD_LOGIC := '0'; SIGNAL fsub_type : STD_LOGIC := '0';
SIGNAL sdp_info : t_sdp_info := ( x"0001", '0', x"00000003", b"01", '0', '0', '0', '0', x"00", x"00", x"00", x"00", x"0000", x"0000"); SIGNAL sdp_info : t_sdp_info := ( x"0001", '0', x"00000003", b"01", '0', '0', '0', '0', x"00", x"00", x"00", x"00", x"0000", x"0000");
-- signals used for response of mm bus
SIGNAL mm_natural_response : NATURAL;
-- signals used for starting processes -- signals used for starting processes
SIGNAL wr_data : STD_LOGIC_VECTOR(c_ram_buf.dat_w-1 DOWNTO 0); SIGNAL ram_wr_data : STD_LOGIC_VECTOR(c_ram_buf.dat_w-1 DOWNTO 0);
SIGNAL wr_addr : STD_LOGIC_VECTOR(c_ram_buf.adr_w-1 DOWNTO 0); SIGNAL ram_wr_addr : STD_LOGIC_VECTOR(c_ram_buf.adr_w-1 DOWNTO 0);
SIGNAL wr_en : STD_LOGIC; SIGNAL ram_wr_en : STD_LOGIC;
SIGNAL init_ram_done: STD_LOGIC := '0'; SIGNAL init_ram_done: STD_LOGIC := '0';
SIGNAL rx_bsn : NATURAL := 0;
SIGNAL rx_data_id : NATURAL := 0;
BEGIN BEGIN
dp_rst <= '1', '0' AFTER c_dp_clk_period*7; dp_rst <= '1', '0' AFTER c_dp_clk_period*7;
dp_clk <= (NOT dp_clk) OR tb_end AFTER c_dp_clk_period/2; dp_clk <= (NOT dp_clk) OR tb_end AFTER c_dp_clk_period/2;
...@@ -123,117 +141,163 @@ BEGIN ...@@ -123,117 +141,163 @@ BEGIN
-- fill ram with data, data is same as address number. -- fill ram with data, data is same as address number.
p_mm_statistics_ram : PROCESS p_mm_statistics_ram : PROCESS
VARIABLE addr_cnt : NATURAL := 0;
BEGIN BEGIN
wr_en <= '0'; ram_wr_en <= '0';
-- initialyze -- initialyze
proc_common_wait_until_low(mm_clk, mm_rst); proc_common_wait_until_low(mm_clk, mm_rst);
proc_common_wait_some_cycles(mm_clk, 10); proc_common_wait_some_cycles(mm_clk, 10);
FOR i IN 0 TO c_ram_buf.nof_dat-1 LOOP FOR i IN 0 TO c_ram_buf.nof_dat-1 LOOP
wr_addr <= TO_UVEC(addr_cnt, c_ram_buf.adr_w); ram_wr_addr <= TO_UVEC(i, c_ram_buf.adr_w);
wr_data <= TO_UVEC(addr_cnt, c_ram_buf.dat_w); ram_wr_data <= TO_UVEC(i, c_ram_buf.dat_w);
wr_en <= '1'; ram_wr_en <= '1';
proc_common_wait_some_cycles(dp_clk, 1); proc_common_wait_some_cycles(mm_clk, 1);
addr_cnt := addr_cnt + 1;
END LOOP; END LOOP;
wr_en <= '0'; ram_wr_en <= '0';
init_ram_done <= '1'; init_ram_done <= '1';
WAIT; WAIT;
END PROCESS; END PROCESS;
p_in_sosi : PROCESS p_enable_trigger : PROCESS
BEGIN BEGIN
proc_common_wait_until_high(dp_clk, init_ram_done); proc_common_wait_until_high(mm_clk, init_ram_done);
-- enable common variabel delay -- enable common variabel delay
proc_mem_mm_bus_wr(c_mm_addr_enable, 1, mm_clk, enable_miso, enable_mosi); proc_mem_mm_bus_wr(c_mm_addr_enable, 1, mm_clk, enable_miso, enable_mosi);
proc_common_wait_some_cycles(mm_clk, c_cross_clock_domain_latency); proc_common_wait_some_cycles(mm_clk, c_cross_clock_domain_latency);
--offload_siso <= c_dp_siso_rdy;
proc_common_wait_some_cycles(mm_clk, 1);
FOR i IN 0 TO g_nof_signal_inputs_per_pn LOOP
in_sosi.sync <= '1';
in_sosi.valid <= '1';
in_sosi.sop <= '1';
proc_common_wait_some_cycles(dp_clk, 1);
in_sosi.sync <= '0';
in_sosi.sop <= '0';
proc_common_wait_some_cycles(dp_clk, c_nof_data*c_data_size);
in_sosi.eop <= '1';
proc_common_wait_some_cycles(dp_clk, 1);
in_sosi.eop <= '0';
in_sosi.valid <= '0';
proc_common_wait_some_cycles(dp_clk, 1);
END LOOP;
WAIT; WAIT;
END PROCESS; END PROCESS;
p_mm_reg_stimuli : PROCESS p_in_sosi : PROCESS
BEGIN BEGIN
--enable_mosi <= c_mem_mosi_rst; proc_common_wait_until_low(dp_clk, dp_rst);
--hdr_dat_mosi <= c_mem_mosi_rst; proc_common_wait_some_cycles(dp_clk, 10);
in_sosi.valid <= '1';
WHILE TRUE LOOP
FOR i IN 0 TO c_nof_block_per_sync-1 LOOP
FOR j IN 0 TO c_nof_clk_per_block-1 LOOP
in_sosi.sync <= '0';
in_sosi.sop <= '0';
in_sosi.eop <= '0';
IF i = 0 AND j = 0 THEN
in_sosi.sync <= '1';
END IF;
IF j = 0 THEN
in_sosi.sop <= '1';
in_sosi.bsn <= INCR_UVEC(in_sosi.bsn, 1);
END IF;
IF j = c_nof_clk_per_block-1 THEN
in_sosi.eop <= '1';
END IF;
proc_common_wait_some_cycles(dp_clk, 1);
END LOOP;
END LOOP;
END LOOP;
WAIT;
END PROCESS;
proc_common_wait_until_high(dp_clk, init_ram_done); p_verify : PROCESS(test_offload_sosi, rx_hdr_fields_out, rx_hdr_fields_raw)
proc_common_wait_some_cycles(mm_clk, 100); BEGIN
IF test_offload_sosi.sop = '1' THEN
rx_bsn <= TO_UINT(rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "dp_bsn") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "dp_bsn")));
rx_data_id <= TO_UINT(rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_data_id") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_data_id")));
END IF;
test_offload_siso <= c_dp_siso_rdy;
END PROCESS;
-- station_id, antenna_band_index, observation_id, nyquist_zone_index, f_adc, fsub_type, beam_repositioning_flag, subband_calibrated_flag, O_si, N_si, O_rn, N_rn, block_period, beamlet_scale p_mm_offload : PROCESS
--sdp_info <= ( x"0001", '0', x"00000003", b"01", '0', '0', '0', '0', x"00", x"00", x"00", x"00", x"0000", x"0000"); BEGIN
proc_common_wait_some_cycles(mm_clk, 1); proc_common_wait_until_low(mm_clk, mm_rst);
--in_sosi.sync <= '1'; proc_common_wait_some_cycles(mm_clk, 10);
-- write ethernet destinations via reg_hdr_dat_mosi
proc_mem_mm_bus_wr(c_mm_addr_udp_src_port, TO_UINT(c_udp_src_port), mm_clk, hdr_dat_miso, hdr_dat_mosi);
proc_common_wait_some_cycles(mm_clk, c_cross_clock_domain_latency);
proc_mem_mm_bus_wr(c_mm_addr_ip_src_addr, TO_UINT(c_ip_src_addr), mm_clk, hdr_dat_miso, hdr_dat_mosi);
proc_common_wait_some_cycles(mm_clk, c_cross_clock_domain_latency);
proc_mem_mm_bus_wr(c_mm_addr_eth_src_mac, TO_UINT(c_eth_src_mac), mm_clk, hdr_dat_miso, hdr_dat_mosi);
proc_common_wait_some_cycles(mm_clk, c_cross_clock_domain_latency);
WAIT;
END PROCESS;
proc_common_wait_some_cycles(mm_clk, 100); p_link_offload : PROCESS(offload_sosi, in_sosi)
BEGIN
offload_siso <= c_dp_siso_rst;
IF init_ram_done = '1' THEN
link_offload_sosi <= c_dp_sosi_rst;
link_offload_sosi.data <= offload_sosi.data;
link_offload_sosi.empty <= offload_sosi.empty;
link_offload_sosi.valid <= offload_sosi.valid;
link_offload_sosi.sop <= offload_sosi.sop;
link_offload_sosi.eop <= offload_sosi.eop;
offload_siso <= c_dp_siso_rdy;
END IF;
END PROCESS;
p_dp_end : PROCESS
BEGIN
proc_common_wait_until_high(mm_clk, init_ram_done);
proc_common_wait_some_cycles(dp_clk, 320000);
tb_end <= '1'; tb_end <= '1';
WAIT; WAIT;
END PROCESS; END PROCESS;
u_ram: ENTITY common_lib.common_ram_crw_crw
u_ram: ENTITY common_lib.common_ram_crw_crw_ratio
GENERIC MAP ( GENERIC MAP (
g_ram_a => c_ram_buf, -- settings for port a g_ram => c_ram_buf
g_ram_b => c_ram_buf -- settings for port b
) )
PORT MAP ( PORT MAP (
-- MM read/write port clock domain -- MM write port clock domain
rst_a => mm_rst, rst_a => mm_rst,
clk_a => mm_clk, clk_a => mm_clk,
wr_en_a => master_mosi.wr, wr_en_a => ram_wr_en,
wr_dat_a => master_mosi.wrdata(c_ram_buf.dat_w-1 DOWNTO 0), wr_dat_a => ram_wr_data,
adr_a => master_mosi.address(c_ram_buf.adr_w-1 DOWNTO 0), adr_a => ram_wr_addr,
rd_en_a => master_mosi.rd,
rd_dat_a => master_miso.rddata(c_ram_buf.dat_w-1 DOWNTO 0), -- DP read only port clock domain
rd_val_a => master_miso.rdval, rst_b => dp_rst,
clk_b => dp_clk,
-- ST write only port clock domain adr_b => master_mosi.address(c_ram_buf.adr_w-1 DOWNTO 0),
rst_b => dp_rst, rd_en_b => master_mosi.rd,
clk_b => dp_clk, rd_dat_b => master_miso.rddata(c_ram_buf.dat_w-1 DOWNTO 0),
wr_en_b => wr_en, rd_val_b => master_miso.rdval
wr_dat_b => wr_data,
adr_b => wr_addr,
rd_en_b => '0',
rd_dat_b => OPEN,
rd_val_b => OPEN
); );
p_test_offload : PROCESS(offload_sosi, in_sosi) u_rx : ENTITY dp_lib.dp_offload_rx
BEGIN GENERIC MAP (
offload_siso <= c_dp_siso_rst; g_nof_streams => 1,
IF init_ram_done = '1' THEN g_data_w => c_word_w,
test_offload_sosi <= c_dp_sosi_rst; g_hdr_field_arr => c_sdp_stat_hdr_field_arr,
test_offload_sosi.data <= offload_sosi.data; g_remove_crc => FALSE,
test_offload_sosi.empty <= offload_sosi.empty; g_crc_nof_words => 0
test_offload_sosi.valid <= offload_sosi.valid; )
test_offload_sosi.sop <= offload_sosi.sop; PORT MAP (
test_offload_sosi.eop <= offload_sosi.eop; mm_rst => mm_rst,
mm_clk => mm_clk,
offload_siso <= c_dp_siso_rdy;
END IF; dp_rst => dp_rst,
END PROCESS; dp_clk => dp_clk,
reg_hdr_dat_mosi => offload_rx_hdr_dat_mosi,
reg_hdr_dat_miso => offload_rx_hdr_dat_miso,
snk_in_arr(0) => link_offload_sosi,
snk_out_arr(0) => link_offload_siso,
src_out_arr(0) => test_offload_sosi,
src_in_arr(0) => test_offload_siso,
hdr_fields_out_arr(0) => rx_hdr_fields_out,
hdr_fields_raw_arr(0) => rx_hdr_fields_raw
);
-- SDP info -- SDP info
u_dut: ENTITY work.sdp_statistics_offload u_dut: ENTITY work.sdp_statistics_offload
GENERIC MAP ( GENERIC MAP (
g_statistics_type => "SST", g_statistics_type => "SST",
g_offload_time => 0, g_offload_time => 500,
g_beamset_id => 0 g_beamset_id => 0
) )
PORT MAP ( PORT MAP (
......
libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
+ 2
− 2
View file @ fdc93de7
...@@ -42,7 +42,7 @@ ENTITY dp_block_from_mm IS ...@@ -42,7 +42,7 @@ ENTITY dp_block_from_mm IS
rst : IN STD_LOGIC; rst : IN STD_LOGIC;
clk : IN STD_LOGIC; clk : IN STD_LOGIC;
start_pulse : IN STD_LOGIC; start_pulse : IN STD_LOGIC;
start_address : IN NATURAL RANGE 0 TO g_step_size * g_nof_data; start_address : IN NATURAL;
mm_done : OUT STD_LOGIC; mm_done : OUT STD_LOGIC;
mm_mosi : OUT t_mem_mosi; mm_mosi : OUT t_mem_mosi;
mm_miso : IN t_mem_miso; mm_miso : IN t_mem_miso;
...@@ -82,7 +82,7 @@ BEGIN ...@@ -82,7 +82,7 @@ BEGIN
out_sosi.sop <= r.sop; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.sop can be used for output sop out_sosi.sop <= r.sop; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.sop can be used for output sop
out_sosi.eop <= r.eop; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.eop can be used for output eop out_sosi.eop <= r.eop; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.eop can be used for output eop
mm_done <= d.eop; mm_done <= r.eop;
p_reg : PROCESS(rst, clk) p_reg : PROCESS(rst, clk)
BEGIN BEGIN
......
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