Correct timing of info_sosi, especially to avoid too early for eop fields.

libraries/base/reorder/src/vhdl/reorder_col.vhd

@@ -111,6 +111,7 @@ architecture str of reorder_col is
 
   signal info_sop_wr_en   : std_logic_vector(c_info_nof_pages - 1 downto 0);
   signal info_eop_wr_en   : std_logic_vector(c_info_nof_pages - 1 downto 0);
+  signal info_sosi_paged  : t_dp_sosi;
   signal info_sosi        : t_dp_sosi;
 
   signal store_mosi       : t_mem_mosi;
@@ -123,12 +124,10 @@ architecture str of reorder_col is
   signal select_mosi      : t_mem_mosi := c_mem_mosi_rst;
   signal select_miso      : t_mem_miso := c_mem_miso_rst;
 
+  signal retrieve_info_sosi : t_dp_sosi;
   signal retrieve_sosi      : t_dp_sosi;
   signal retrieve_siso      : t_dp_siso;
 
-  signal ss_sosi          : t_dp_sosi;
-  signal ss_siso          : t_dp_siso;
-
 begin
 
   -----------------------------------------------------------------------------
@@ -241,22 +240,6 @@ begin
     output_siso    => retrieve_siso
   );
 
-  u_rl : entity dp_lib.dp_latency_adapter  -- defaults to wires when c_output_rl = c_retrieve_lat
-  generic map (
-    g_in_latency   => c_retrieve_lat,
-    g_out_latency  => c_output_rl
-  )
-  port map (
-    rst          => dp_rst,
-    clk          => dp_clk,
-    -- ST sink
-    snk_out      => retrieve_siso,
-    snk_in       => retrieve_sosi,
-    -- ST source
-    src_in       => ss_siso,
-    src_out      => ss_sosi
-  );
-
   -- Page delay the input_sosi info (sync, BSN, channel at sop and err, empty at eop) and combine
   -- it with the retrieved SS data to get the output_sosi.
   info_sop_wr_en <= input_sosi.sop & store_done;
@@ -275,11 +258,30 @@ begin
     -- ST sink
     snk_in      => input_sosi,
     -- ST source
-    src_out     => info_sosi
+    src_out     => info_sosi_paged
   );
 
-  output_sosi <= func_dp_stream_combine_info_and_data(info_sosi, ss_sosi);
-  ss_siso     <= output_siso;
+  -- Account for retrieve rd latency is 1, for sop related info it is not
+  -- critical that it arrives early, but for eop related info it is.
+  info_sosi <= info_sosi_paged when rising_edge(dp_clk);
+  retrieve_info_sosi <= func_dp_stream_combine_info_and_data(info_sosi, retrieve_sosi);
+
+  -- Adapt output ready latency (RL), defaults to wires when c_output_rl = c_retrieve_lat
+  u_rl : entity dp_lib.dp_latency_adapter
+  generic map (
+    g_in_latency   => c_retrieve_lat,
+    g_out_latency  => c_output_rl
+  )
+  port map (
+    rst          => dp_rst,
+    clk          => dp_clk,
+    -- ST sink
+    snk_out      => retrieve_siso,
+    snk_in       => retrieve_info_sosi,
+    -- ST source
+    src_in       => output_siso,
+    src_out      => output_sosi
+  );
 
 end str;
 

libraries/base/reorder/src/vhdl/reorder_col_select.vhd

@@ -93,6 +93,7 @@ architecture str of reorder_col_select is
 
   signal info_sop_wr_en   : std_logic_vector(c_info_nof_pages - 1 downto 0);
   signal info_eop_wr_en   : std_logic_vector(c_info_nof_pages - 1 downto 0);
+  signal info_sosi_paged  : t_dp_sosi;
   signal info_sosi        : t_dp_sosi;
 
   signal store_mosi       : t_mem_mosi;
@@ -227,9 +228,12 @@ begin
     -- ST sink
     snk_in      => input_sosi,
     -- ST source
-    src_out     => info_sosi
+    src_out     => info_sosi_paged
   );
 
+  -- Account for retrieve rd latency is 1, for sop related info it is not
+  -- critical that it arrives early, but for eop related info it is.
+  info_sosi <= info_sosi_paged when rising_edge(dp_clk);
   output_sosi <= func_dp_stream_combine_info_and_data(info_sosi, retrieve_sosi);
 
 end str;