Added multi testbench tb_tb_tech_eth_10g.vhd.

libraries/technology/eth_10g/hdllib.cfg

@@ -14,6 +14,7 @@ synth_files =
 test_bench_files =
     tb_tech_eth_10g.vhd
     tb_tech_eth_10g_ppm.vhd
+    tb_tb_tech_eth_10g.vhd
     
 modelsim_search_libraries =
     altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver  stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver

libraries/technology/eth_10g/tb_tb_tech_eth_10g.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Multi testbench for tech_eth_10g the 10G Ethernet IP technology wrapper.
+-- Description:
+-- Usage:
+--   > as 5
+--   > run -all
+
+LIBRARY IEEE, technology_lib, tech_pll_lib, tech_mac_10g_lib;
+USE IEEE.std_logic_1164.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE tech_mac_10g_lib.tb_tech_mac_10g_pkg.ALL;
+USE tech_pll_lib.tech_pll_component_pkg.ALL;
+
+
+ENTITY tb_tb_tech_eth_10g IS
+END tb_tb_tech_eth_10g;
+
+
+ARCHITECTURE tb OF tb_tb_tech_eth_10g IS
+
+  CONSTANT c_644       : TIME := tech_pll_clk_644_period;
+  CONSTANT c_156       : TIME := 6.4 ns;
+  CONSTANT c_data_type : NATURAL := c_tb_tech_mac_10g_data_type_symbols;
+  
+BEGIN
+
+-- g_technology              : NATURAL := c_tech_select_default;
+-- g_sim_level               : NATURAL := 0;     -- 0 = use IP; 1 = use fast serdes model
+-- g_ref_clk_644_period      : TIME := tech_pll_clk_644_period;  -- for 10GBASE-R
+-- g_ref_clk_156_period      : TIME := 6.4 ns;                   -- for XAUI
+-- g_data_type               : NATURAL := c_tb_tech_mac_10g_data_type_symbols;
+-- g_verify_link_recovery    : BOOLEAN := TRUE;
+-- g_link_status_check       : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0) := "11";
+-- g_use_serial_rx_in        : BOOLEAN := FALSE 
+
+  u_tech_eth_10g : ENTITY work.tb_tech_eth_10g GENERIC MAP (c_tech_select_default, 0, c_644, c_156, c_data_type, TRUE, "11", FALSE);
+  u_sim_eth_10g  : ENTITY work.tb_tech_eth_10g GENERIC MAP (c_tech_select_default, 1, c_644, c_156, c_data_type, TRUE, "11", FALSE);
+  
+END tb;