Added mon_latency test to tb

libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd

@@ -108,7 +108,7 @@ ARCHITECTURE rtl OF dp_bsn_monitor_v2 IS
   SIGNAL nof_err                     : STD_LOGIC_VECTOR(c_cnt_sop_w-1 DOWNTO 0);
   SIGNAL cnt_valid                   : STD_LOGIC_VECTOR(c_cnt_valid_w-1 DOWNTO 0);
   SIGNAL nof_valid                   : STD_LOGIC_VECTOR(c_cnt_valid_w-1 DOWNTO 0);
-  SIGNAL cnt_lateny                  : STD_LOGIC_VECTOR(c_cnt_latency_w-1 DOWNTO 0);
+  SIGNAL cnt_latency                  : STD_LOGIC_VECTOR(c_cnt_latency_w-1 DOWNTO 0);
   SIGNAL latency                     : STD_LOGIC_VECTOR(c_cnt_latency_w-1 DOWNTO 0);
 
   SIGNAL i_mon_ready_stable          : STD_LOGIC;
@@ -120,6 +120,12 @@ ARCHITECTURE rtl OF dp_bsn_monitor_v2 IS
   SIGNAL i_mon_latency               : STD_LOGIC_VECTOR(c_cnt_latency_w-1 DOWNTO 0);
   SIGNAL i_current_bsn               : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0);
 
+  SIGNAL inv_mon_bsn_at_sync         : STD_LOGIC_VECTOR(c_bsn_w-1 DOWNTO 0) := (OTHERS => '1');
+  SIGNAL inv_mon_nof_sop             : STD_LOGIC_VECTOR(c_cnt_sop_w-1 DOWNTO 0) := (OTHERS => '1');
+  SIGNAL inv_mon_nof_err             : STD_LOGIC_VECTOR(c_cnt_sop_w-1 DOWNTO 0) := (OTHERS => '1');
+  SIGNAL inv_mon_nof_valid           : STD_LOGIC_VECTOR(c_cnt_valid_w-1 DOWNTO 0) := (OTHERS => '1');
+  SIGNAL inv_mon_latency             : STD_LOGIC_VECTOR(c_cnt_latency_w-1 DOWNTO 0) := (OTHERS => '1');
+
   SIGNAL sync_timeout_cnt            : STD_LOGIC_VECTOR(c_sync_timeout_w-1 DOWNTO 0);
   SIGNAL sync_timeout                : STD_LOGIC;
   SIGNAL sync_timeout_n              : STD_LOGIC;
@@ -142,11 +148,11 @@ BEGIN
   mon_sync_timeout        <= sync_timeout;
   mon_ready_stable        <= i_mon_ready_stable;
   mon_xon_stable          <= i_mon_xon_stable;
-  mon_bsn_at_sync         <= i_mon_bsn_at_sync  WHEN sync_timeout='0' ELSE (OTHERS=>'1');
-  mon_nof_sop             <= i_mon_nof_sop      WHEN sync_timeout='0' ELSE (OTHERS=>'1');
-  mon_nof_err             <= i_mon_nof_err      WHEN sync_timeout='0' ELSE (OTHERS=>'1');
-  mon_nof_valid           <= i_mon_nof_valid    WHEN sync_timeout='0' ELSE (OTHERS=>'1');
-  mon_latency             <= i_mon_latency      WHEN sync_timeout='0' ELSE (OTHERS=>'1');
+  mon_bsn_at_sync         <= i_mon_bsn_at_sync  WHEN sync_timeout='0' ELSE inv_mon_bsn_at_sync;
+  mon_nof_sop             <= i_mon_nof_sop      WHEN sync_timeout='0' ELSE inv_mon_nof_sop;
+  mon_nof_err             <= i_mon_nof_err      WHEN sync_timeout='0' ELSE inv_mon_nof_err;
+  mon_nof_valid           <= i_mon_nof_valid    WHEN sync_timeout='0' ELSE inv_mon_nof_valid;
+  mon_latency             <= i_mon_latency      WHEN sync_timeout='0' ELSE inv_mon_latency;
   
   nxt_mon_evt          <= sync OR sync_timeout_revt;
   nxt_mon_ready_stable <= ready_stable WHEN sync='1' ELSE i_mon_ready_stable;

libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd

@@ -99,7 +99,7 @@ BEGIN
 
   gen_stream : FOR i IN 0 TO g_nof_streams-1 GENERATE
       
-    u_reg : ENTITY work.dp_bsn_monitor_reg
+    u_reg : ENTITY work.dp_bsn_monitor_reg_v2
     GENERIC MAP (
       g_cross_clock_domain => g_cross_clock_domain
     )
@@ -129,7 +129,7 @@ BEGIN
       mon_latency             => mon_latency_arr(i)
     );
     
-    u_mon : ENTITY work.dp_bsn_monitor
+    u_mon : ENTITY work.dp_bsn_monitor_v2
     GENERIC MAP (
       g_sync_timeout  => g_sync_timeout,
       g_error_bi      => g_error_bi

libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd

@@ -57,6 +57,7 @@ ARCHITECTURE tb OF tb_dp_bsn_monitor_v2 IS
   CONSTANT c_sync_offset         : NATURAL := 0;
   CONSTANT c_sync_timeout        : NATURAL := c_frame_len*c_sync_period;
   CONSTANT c_nof_repeat          : NATURAL := g_nof_sync * c_sync_period + 1;
+  CONSTANT c_ref_sync_latency    : NATURAL := 7;
   
   -- Error control
   CONSTANT c_skip_sync_nr        : INTEGER := -1;  -- use e.g. 5 >= 0 to introduce a sync timeout at that sync interval 5 (causes missing sinc error by proc_dp_verify_sync), use -1 to disable skipping a sync
@@ -75,7 +76,7 @@ ARCHITECTURE tb OF tb_dp_bsn_monitor_v2 IS
   SIGNAL in_en                   : STD_LOGIC := '1';
   SIGNAL in_siso                 : t_dp_siso := c_dp_siso_rdy;
   SIGNAL in_sosi                 : t_dp_sosi;
-  SIGNAL sync_in                 : STD_LOGIC := '0';
+  SIGNAL ref_sync                : STD_LOGIC := '0';
   
   -- Output
   SIGNAL out_siso                : t_dp_siso;
@@ -111,6 +112,7 @@ ARCHITECTURE tb OF tb_dp_bsn_monitor_v2 IS
   SIGNAL expected_nof_sop      : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
   SIGNAL expected_nof_err      : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
   SIGNAL expected_nof_valid    : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+  SIGNAL expected_latency      : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
 
 BEGIN
 
@@ -185,6 +187,7 @@ BEGIN
   expected_nof_sop     <= TO_UVEC(            c_sync_period, c_word_w);
   expected_nof_err     <= TO_UVEC(                c_nof_err, c_word_w);
   expected_nof_valid   <= TO_UVEC(c_frame_len*c_sync_period, c_word_w);
+  expected_latency     <= TO_UVEC(       c_ref_sync_latency, c_word_w);
   
   ------------------------------------------------------------------------------
   -- SISO FLOW CONTROL GENERATION
@@ -252,23 +255,18 @@ BEGIN
     WAIT;
   END PROCESS;
 
-  p_sync_in_stimuli : PROCESS
+  p_ref_sync_stimuli : PROCESS
   BEGIN
-    sync_in <= '0';
+    ref_sync <= '0';
     proc_common_wait_until_low(clk, rst);
-    proc_common_wait_some_cycles(clk, 25); --on SOP
-    sync_in <= '1';
-    proc_common_wait_some_cycles(clk, 1);
-    sync_in <= '0';
-    proc_common_wait_some_cycles(clk, 38); --on EOP
-    sync_in <= '1';
-    proc_common_wait_some_cycles(clk, 1);
-    sync_in <= '0';
-    proc_common_wait_some_cycles(clk, 67); -- random 
-    sync_in <= '1';
-    proc_common_wait_some_cycles(clk, 1);
-    sync_in <= '0';
-
+    proc_common_wait_until_hi_lo(clk, in_sosi.sync);
+    proc_common_wait_some_cycles(clk, (c_sync_timeout-2-c_ref_sync_latency)); 
+    FOR I IN 0 TO c_nof_repeat-2 LOOP
+      ref_sync <= '1';
+      proc_common_wait_some_cycles(clk, 1);
+      ref_sync <= '0';
+      proc_common_wait_some_cycles(clk, c_sync_timeout-1); 
+    END LOOP;
     WAIT;
   END PROCESS;
 
@@ -305,6 +303,7 @@ BEGIN
   proc_dp_verify_value(e_equal, clk, verify_done, expected_nof_sop,   mon_nof_sop);
   proc_dp_verify_value(e_equal, clk, verify_done, expected_nof_err,   mon_nof_err);
   proc_dp_verify_value(e_equal, clk, verify_done, expected_nof_valid, mon_nof_valid);
+  proc_dp_verify_value(e_equal, clk, verify_done, expected_latency,   mon_latency);
   
   
   ------------------------------------------------------------------------------
@@ -323,7 +322,7 @@ BEGIN
     -- ST interface
     in_siso                 => out_siso,
     in_sosi                 => in_sosi,
-    sync_in                 => sync_in,
+    ref_sync                => ref_sync,
     
     -- MM interface
     -- . control
@@ -338,8 +337,7 @@ BEGIN
     mon_nof_sop             => mon_nof_sop,
     mon_nof_err             => mon_nof_err,
     mon_nof_valid           => mon_nof_valid,
-    mon_latency             => mon_latency,
-
+    mon_latency             => mon_latency
   );
     
 END tb;