Added the check if g_check_input_sync = True for using the input sync to

reset the counter.

libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd

@@ -136,9 +136,8 @@
 -- . Using g_check_input_sync=True is similar to using a dp_sync_checker in
 --   front of this dp_block_gen_valid_arr. However the advantage of
 --   dp_sync_checker is that it provides monitoring and control via MM.
--- . If snk_in.sync is always '0', sync out is generated at g_nof_blk_per_sync.
---   Otherwise, the output sync is also derived from snk_in.sync to allow for
---   a fractional amount of blocks per sync period.
+-- . If g_check_input_sync = True, te output sync is derived from snk_in.sync to 
+--   allow for a fractional amount of blocks per sync period.
 
 LIBRARY IEEE, common_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
@@ -274,14 +273,14 @@ BEGIN
             -- maintain blk_cnt for output sync interval, the blk_cnt is the local bsn that wraps at every sync
             IF r.blk_cnt>=g_nof_blk_per_sync-1 THEN
               nxt_r.blk_cnt <= 0;
-            ELSIF snk_in.sync = '1' THEN 
+            ELSIF g_check_input_sync AND snk_in.sync = '1' THEN 
               nxt_r.blk_cnt <= 1;
             ELSE
               nxt_r.blk_cnt <= r.blk_cnt+1;
             END IF;
 
             -- create local sync and pass on input bsn at local sync
-            IF r.blk_cnt=0 OR snk_in.sync = '1' THEN    -- output sync starts at first input valid
+            IF r.blk_cnt=0 OR (g_check_input_sync AND snk_in.sync = '1') THEN    -- output sync starts at first input valid
               nxt_r.reg_sosi.sync <= '1';               -- output sync for this block
               nxt_r.reg_sosi.bsn  <= in_sosi.bsn;       -- output input bsn at sync
             ELSE